Increasingly, the ability to address transistor aging is showing up in EDA tools and IP.
Given the ever increasing challenge of designing high-reliability ICs – especially for automotive, medical, industrial, and aerospace and defense applications – the inclusion of aging analysis capabilities is on the rise in EDA tools as well as design IP.
The issue comes down to predictability of devices as they operate. As discussed in, “Taming NBTI To Improve Device Reliability,” there are a variety of impacts on a device from shrinking geometries in advanced nodes including such phenomenon as negative-bias temperature instability, hot carrier injection, and time dependent dielectric breakdown. Protecting a device from these effects is no small task so various parties across the semiconductor design and manufacturing ecosystem, as well as academia, are examining what can be done on either or both the design and process side.
From the EDA perspective, whereas five years ago transistor aging was a topic for a technical expert, today, it is more common to see aging analysis included in design IP and EDA design tools to equip engineering teams properly for the challenges of high reliability applications.
What is your experience with accounting for aging in your design today? Please feel free to comment below and share your observations.
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Very good article pointing to an important aspect which is often neglected by the IP providers.
We at eSilicon have been considering the effect of aging right through the chip design phase. Since the device performance degrades with aging, the design phase adds adequate margin to ensure that the chip will meet its target performance all through its expected lifespan. The eSilicon IP also considers the impact of aging during the design of IP.