How to design interconnects in complex SoCs.
Modern System-on-Chip (SoC) architects are faced with a number of serious challenges. First, the number of Semiconductor Intellectual Property (IP) blocks in SoC designs is growing continuously and increasing design complexity. With IP design reuse becoming more common, the mixing and matching of IP components is further compounding design complexity. Second, sophisticated SoC applications are presenting complex requirements for system Quality-of-Service (QoS) and system bandwidth. Third, a shrinking power envelope is requiring sophisticated power management. Finally, compressed project cycles require faster design time. All of these factors have created a need for automated, high-performance, scalable SoC interconnects.
This white paper examines a fundamentally new way to design SoC interconnects that addresses these complex requirements. To read more, click here.
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