How SMIC improved turnaround time with 90% average utilization at the 65nm and 40nm process nodes.
n today’s semiconductor industry, both the pure-play and independent device manufacturer (IDM) foundries are constantly and rigorously competing for market share. A key feature in their success is the ability to meet or exceed aggressive time-to-market schedules. Leading foundry Semiconductor Manufacturing International Corporation (SMIC) aims to ensure continual improvement in its fab’s turnaround time (TAT), which is challenging given that newer technology nodes and their associated processes are increasing in complexity, and consequently, in their time-to-process. Assessments of runtime data trends at the 65nm and 40nm technology nodes suggested that hardware and software utilization improvements could reduced overall TAT. In this paper, SMIC describes how they achieve just over a 30% aggregate TAT improvement in conjunction with a greater than 90% average utilization of all hardware using the Mentor Graphics Calibre Cluster Manager (CalCM) software.
To download this white paper, click here.
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