Deep Space Design Considerations

The linchpin technology in a deep space telescope is the ability to efficiently convert analog image sensor data into digital data in order to beam home high-resolution images of astronomical objects. The analog-to-digital converters (ADC) must perform flawlessly once deployed, because it is not feasible to drive out 1 million miles into space to fix any problems.

The next-generation successor to the Hubble Space Telescope is the James Webb Space Telescope (JWST). A key element in the JWST is the near-infrared camera (NIRCAM) that contains an electronic imager and signal processing ASIC. The NIRCAM allows the JWST to peer substantially farther through the dark-matter clouds of the extra-galactic universe. It can see farther in time to the epoch of ‘first light’ and to the birth of the very first stars.

Figure 1: An artist’s impression of the deployed JWST in L2 orbit showing the 6.55 m segmented telescope mirror and matching sunshade. (Source: Northrop-Grumman)

Dr. Lanny Lewyn, founder of Lewyn Consulting Incorporated (LCI), won the opportunity to create an x36 19-bit ADC array that is embedded in the imager ASIC. He discusses the unique design requirements of his project.

Circuit and Physical Design Considerations for the ADC

LCI has developed a complete set of dimensionless schematic capture and layout techniques to rapidly port existing and new circuit elements to the fabrication technology selected by for the JWST project.

“I believed that our dimensionless methodology would be the key to LCI completing the circuit and physical design within the timeframe needed to win the JWST sensor competition,” said Dr. Lewyn.

The LCI dimensionless design methodology is based on Gamma rules that use a dimension equal to 1/4 minimum gate width. As a result, this methodology has evolved to meet the stringent gate pitch requirements of DUV lithography and it allows area-efficient physical designs to cover a wide range of processing line widths from 180nm to 28nm.

An ADC that processes signals from an exceptionally wide dynamic range sensor requires extreme linearity requirements. The differential linearity (DL) requirement for the JWST application was a maximum of ½ LSB at the low end of the range. Achieving high image fidelity with the extremely dark background of deep space requires that the ADC has a high DL accuracy (low noise) when the input signal from the imaging detector is just a few electrons. Because the ADC quantization noise contribution is equal to approximately 1/3 “q” step [specifically q/sqrt(12)], the ADC must be designed to a resolution specification of 19-bits in order to keep the 16-bit-equivalent quantization noise well below the level of the other contributors.

Unfortunately, foundry-supplied precision capacitors in process design kits available for most technologies do not have the precision required to achieve 16 +/- 2 bit IL without using digital calibration. Dynamic digital calibration methods for signals with Gaussian distributions will not work with the asymmetrical characteristics typical of deep space image signals. These methods also require extra area and power. For a 10 year mission without cryogenic re-supply, the maximum power allocated for each ADC in the x36 array is 1.5mw.  Most analog CMOS ADCs with resolutions beyond 12-bits require digital calibration throughout the dynamic range. The physical design of the capacitor MSB weighting network elements to achieve the 16-bit IL accuracy requirements without dynamic calibration requires careful attention to every small detail.

According to Dr. Lewyn, “In order to achieve a suitable physical design for the precision capacitor, LCI relied on the simplicity of graphic and array-control features in the Tanner L-Edit tool to layout the complex structure of the capacitor plate layers, external shields, and interconnects. In addition, several layers ancillary to the basic capacitor layout (such as implants) could be generated using the Boolean layer generation features in L-Edit to perform a variety of AND/OR/NOT functions along with the layer resize functions to comply with foundry technology-scale design rules and manufacturing grid constraints at the mask level.”

An important aspect of the physical design was the requirement to minimize the effect on precise capacitance value from lithographic variations local to the individual capacitor layout patterning as well as first and second order effects from process variations across the chip. In order to satisfy all of the design constraints, it was necessary to develop both precise capacitor and MOS device patterns that could allow placement of each in uniform pitch patterns in both X and (as much as possible) Y directions. To satisfy the uniform pitch requirement, a precise capacitor pattern including capacitance layers, shielding, and interconnect, was developed that had a recurrence of precise, multiple of 4 MOS device patterns. In order to fit amplifier, switching, gating, and logic subcircuits into the regularity of the capacitor patterns, a uniform subcircuit width was maintained equal to the pitch of 4 capacitors, or 16 devices.

Figure 2: A section (approximately 20% of the total X-dimension) of the JWST ADC with precise capacitor selection in the X direction.

Performance of the Production ADC Array

For an ADC targeting astronomical research imaging applications, the test results on the production version of the ADC array were outstanding. In order to preserve image quality at the low (black) end of the dynamic range, it was important to achieve a DL of +/- 0.5 LSB at 16-bits. The ADC DL performance was better than +/- 0.3 LSB over the entire dynamic range (Figure 3a). The integral linearity (IL) exceeded the +/- 2 LSB requirement by 0.5 LSB, but only beyond the lower ¼ of the brightness scale (Figure 3b). At this signal level, the quantum statistics of the detector electron collection exceed the ADC IL variation, making the extra 0.5 LSB error at ¼ scale insignificant.

Figure 3A and 3B: Differential linearity (DL) and integral linearity (IL) of the LCI ADC measured at 16-bit “q” intervals.

The ADC was integrated into the imaging ASIC in an x36 array (yellow boundary in Figure 4). In conjunction with the preamp imager electronics, it performed within the image quality noise specification of 5 rms electrons. Because the JWST mission constraints do not allow for servicing, achieving a 1.5mw per-ADC power level was important. At present, the image processing system has been qualified to NASA Technology Readiness Level 6 (TRL-6) for the 2018 JWST mission.

Figure 4: The RSC (now Teledyne) electronic image and signal processing ASIC including the LCI x36 ADC array (in the yellow boundary).

For more information about the design of this ADC for use on the James Web Space Telescope, see the case study here.