Aveek Sarkar

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Aveek Sarkar is vice president of engineering at Synopsys.

Author's Latest Posts

Addressing IC Hyperconvergence Design Challenges
By Aveek Sarkar - 11 Mar, 2021 - Comments: 0

Recently in an article titled “A Renaissance for Semiconductors,” my colleague Michael Sanie highlighted some of the trends that are driving next-generation product development. He detailed how designs targeting new applications are innovating through a combination of advanced process node technologies and heterogeneous integration of stacked die/3D/2.5D systems. Additionally, advanced vert... » read more

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

FinFET Based Designs: Reliability Verification Implications
By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

FinFET-Based Designs: Package Model Considerations
By Aveek Sarkar - 12 Jun, 2014 - Comments: 0

The use of FinFET devices in next-generation high-performance, low-power designs is a fundamental shift that is happening in the semiconductor industry. These devices through their smaller sizes, tighter Vth control and higher drive strengths enable higher performance and increased integration while reducing overall energy consumption. But along with their advantages these devices introduce and... » read more

FinFET-Based Designs: Power Sign-off Considerations
By Aveek Sarkar - 08 May, 2014 - Comments: 0

FinFET devices can operate at ultra-low sub-1V nominal supply voltage levels without impacting their delays. This allows for low power, higher performance designs needed for many of todays’ applications. These devices also have considerably higher drive strengths, allowing faster operating speeds. However, this can result in more localized di/dt current scenarios, and when coupled with more r... » read more

FinFET Based Designs: Power Analysis Considerations
By Aveek Sarkar - 10 Apr, 2014 - Comments: 2

Design teams working on mobile, computing, networking and other low power, high performance IPs and SoCs are migrating to FinFET-based technologies. However the benefits from their smaller sizes and the ability to deliver consistent performance at ultra-low sub-1V nominal supply voltage levels is outweighed by the worsening of power noise and reliability. As mentioned in an earlier blog on Powe... » read more

Power Noise And Reliability Sign-off For The Sub-20nm FinFET Era
By Aveek Sarkar - 16 Jan, 2014 - Comments: 1

There is a greater focus on power noise and reliability simulations and sign-off as the complexity of SoC designs continue to increase with 100+ different voltage islands, clock and power gating techniques, and multiple IPs each operating on different clock and power domains, etc. The technology node migration from 40nm to 20nm is driving requirements for electro-migration (EM) and reliability ... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 13 Jun, 2013 - Comments: 0

In the first two parts of this series, we reviewed the challenges design teams face as they grapple with increasing power consumption, tighter schedules and the drive to reduce costs. Both a top-down and a bottom-up analysis framework were proposed to help control these challenges. In part 2 of this series, specific challenges were outlined including power budgeting, power and signal integrity,... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 09 May, 2013 - Comments: 0

Power efficiency, unrealistic schedules, and cost-down considerations are increasingly the top challenges design teams must meet to deliver next generation electronic systems, whether it is for the mobile, server, or automotive market. In addition, a successful chip tapeout does not guarantee the eventual end-product’s success—there are many variables to take into account. In the first p... » read more

Challenges In IC And Electronic Systems Verification
By Aveek Sarkar - 11 Apr, 2013 - Comments: 0

By Aveek Sarkar Designing successful electronic systems that can meet the needs of a challenging and quickly evolving mobile market requires design teams to solve critical problems such as power efficiency, unrealistic schedules, and cost-down considerations. In this first of a three-part series, we will look at these challenges. Part 1: The Growing Challenges Designing electronic systems ... » read more

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