FinFET Based Designs: Reliability Verification Implications

Electromigration and ESD become much bigger challenges with 3D transistors.

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Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overall switching is reduced especially when chip is in idle mode.

Physical-aware RTL power analysis becomes the entry and starting point for addressing this challenge. These RTL power analyses drive power reduction opportunities that are more meaningful and have wider impact on the final gate-level netlist than if they were based on pure logic and switching analyses.

For sub-20mn finFET based designs, voltage drop analysis has taken a different requirement of its own. Accuracy of the analysis, which is achieved by considering both the package and the chip in their entirety becomes critical as the margins continue to shrink from reduced supply voltage levels (sub-700mV) and higher levels of noise (100mV+). Inclusion of a detailed, distributed and ‘physical’ package model in the SoC dynamic voltage drop simulations, along with co-visualization capabilities, becomes a necessity for SoC engineers to truly consider the package as an integral part of their chips.

Unlike timing or DRC/LVS checks, which are ‘static’ and fully deterministic in nature, power is a statistical problem. It changes over time depending on the operating mode, environmental conditions and system level interactions. Attempts to ‘bound’ voltage drop analysis through “static” analysis methods, such as those used in timing, can result in significant overdesign both in the chip and in the package or show up as electrical problems during bring-up or in the field. Given power’s ‘statistical’ nature, power noise analysis needs to expand sign-off coverage through multiple different angles – including grid robustness analysis early in the design process, the use of RTL vectors for power and voltage drop analysis to identify issues in real use cases, and the use of statistical methods to highlight areas of likely failures. These simulation methods have to be complemented with design analytics techniques that mine data from design database through simulation to provide guidance in improving areas of possible failures or reducing the over-design in other regions.

Finally, I will discuss one of the most critical issues, which is the long-term reliability of these extremely sensitive devices and the on-chip wire/vias. Electro-migration (EM) is a well-understood topic and has always been a key criteria for design teams. Traditionally, teams focused on mobile and other consumer application have not considered EM as a limiting factor since their products typically had life expectancy of no more than five years. However, as mobile SoCs lead the charge in the finFET transition, and as the same ICs (or their re-incarnations) show up in mission-critical applications such as automobiles, EM analysis moves front and center—and oftentimes determines the size of the drivers that can be used or the minimum size of the wires/vias that can be placed across the chip. EM requirements severely impact the routing resources, and in turn affect the timing closure.

As seen from foundry data, for sub-20nm nodes the EM limits for vias are generally 70% of what they were for prior technologies while finFET device current levels are 25% to 30% higher. Additionally, locally generated heat from the fins worsens the thermal signature of the chip, which further exacerbates the current density issues. Hence, an accurate and well-defined EM methodology from IP to SoC sign-off to chip-package-system co-design becomes critical for a quicker path to design closure.

EM analysis has to start from the design of the IPs, including standard cells. One has to simulate every standard cell and IP (memories, analog) for both power and signal line EM across various operating modes. Given the sheer number of IPs, it is important to have an automated checking methodology that not only scans through the layouts considering various PVT and input slope/output load conditions, but also create models that can be used for SoC level verification.

At the SoC level, EM analysis must be performed for both power and signal lines, especially for clock nets. Many design teams believe that EM of their design is fine because they added the ‘required’ number of vias in every stack or met the ‘required’ wire width. However, localized clustering of high-power devices or improper power grid routing, especially at block boundaries, create current congestion issues that exacerbate EM issues, which can cause failure scenarios.

Given the power consumption and more importantly power density trends, self-heat effects for finFETs, and the limited cooling opportunities in hand-held mobile devices, a comprehensive chip-package-system thermal analysis methodology has become a necessity. This flow should take chip level power data for various operating modes along with package/system information to generate thermal maps for the chip, package and system. Additionally, it should feed the chip thermal data back to the on-die EM analysis to redefine the current flow, EM limits, and resulting violations.

Electrostatic discharge (ESD) is also coming to the forefront of reliability challenges. Figure 1 highlights some of the ways ESD events can cause failures including damage to the devices or to the wires/vias from high instantaneous current flow. Based on industry data on field return and testing, 40% of failures are from device breakdown, 30% to 40% are from interconnect failures and about 15% are from cross-domain ESD issues.

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Fig. 1: Various ESD failure scenarios for today’s advanced SoCs.
Adding traditional ESD protection devices is not possible in finFET technology, so there is a shift to using larger and less effective diodes. To prevent ESD induced failures, SoC and ESD designers have to pay close attention on the design and size of these devices, their placement and connectivity. Traditional approaches of using ‘design guidelines’ or ‘plot checks’ are too limiting and error prone. Layout-based simulation techniques that consider the parasitics of the on-chip interconnects, incorporate their connectivity to the ESD protection devices, and predict the flow of current in these wires during an ESD event, are required to identify, isolate and fix any possible failure scenarios. These simulations have to be done at the full-chip level incorporating the package and its layout in the analysis for a complete picture.

In conclusion, finFETs will help continue the low-power innovations that are changing our lives. As ICs based on this technology become mainstream, the challenges listed in this blog series will have to be factored into a design process to ensure that design teams can fully benefit from this remarkable device while avoiding the pitfalls that it brings.