tag: Leakage

Hardware Security: New Mathematical Model To Quantify Information Flow in Digital Circuits For Different Attack Models (RWTH Aachen)
By Technical Paper Link - 06 Dec, 2022 - Comments: 0

A new technical paper titled "Quantitative Information Flow for Hardware: Advancing the Attack Landscape" was published by researchers at RWTH Aachen University. Abstract: "Security still remains an afterthought in modern Electronic Design Automation (EDA) tools, which solely focus on enhancing performance and reducing the chip size. Typically, the security analysis is conducted by hand, l... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Identifying DRAM Failures Caused By Leakage Current And Parasitic Capacitance
By Taeyon (TY) Oh - 03 Feb, 2020 - Comments: 0

Leakage current has been a leading cause of device failure in DRAM design, starting with the 20nm technology node. Problems with leakage current in DRAM design can lead to reliability issues, even when there are no obvious structural abnormalities in the underlying device. Leakage current has become a critically important component in DRAM device design. Fig. 1 (a) DRAM Memory Cell, (b) GI... » read more

GDDR6 Drilldown: Applications, Tradeoffs And Specs
By Ed Sperling - 15 Nov, 2019 - Comments: 0

Frank Ferro, senior director of product marketing for IP cores at Rambus, drills down on tradeoffs in choosing different DRAM versions, where GDDR6 fits into designs versus other types of DRAM, and how different memories are used in different vertical markets. » read more

Using Less Power At The Same Node
By Brian Bailey - 14 Mar, 2019 - Comments: 0

Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Power Issues Rising For New Applications
By Ann Mutschler - 21 Jan, 2019 - Comments: 0

Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past. While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several re... » read more

Thermal Impact On Reliability At 7/5nm
By Ed Sperling - 28 Sep, 2018 - Comments: 0

Haroon Chaudhri, director of RedHawk Analysis Fusion at Synopsys, talks about why thermal analysis is shifting left in the design cycle and why this is so critical at the most advanced process nodes. https://youtu.be/wjkrEFLb2vY » read more

Estimating MOSFET Leakage From Low-Cost, Low-Resolution Fast Parametric Test
By PDF Solutions - 19 Jul, 2018 - Comments: 0

A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient tran... » read more

22nm Process Technology
By Ed Sperling - 19 Jul, 2018 - Comments: 0

Jamie Shaeffer, senior director of product line management at GlobalFoundries, talks about how FD-SOI compares with bulk technologies, where it will be used and why, and future stacking options. https://youtu.be/2i7GJRxcNRs » read more

System-Level Power Modeling Takes Root
By Ann Mutschler - 10 May, 2018 - Comments: 0

Power, heat, and their combined effects on aging and reliability, are becoming increasingly critical variables in the design of chips that will be used across a variety of new and existing markets. As more processing moves to edge, where sensors are generating a tsunami of data, there are a number of factors that need to be considered in designs. On one side, power budgets need to reflect th... » read more

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