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A Complete System-Level Security Verification Methodology
By Cadence - 04 Mar, 2020 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Transient Thermal Analysis For M.2 SSD Thermal Throttling: Detailed CFD Model vs Network-Based Model
By Cadence - 15 Jan, 2020 - Comments: 0

Solid State Drive (SSD) technology continues to advance toward smaller footprints with higher bandwidth and adoption of new I/O interfaces in the PC market segment. Power performance requirements are tightening in the design process to address specific requirement along with the development of SSD technology. To meet this aggressive requirement of performance, one major issue is thermal throttl... » read more

Building A State-of-the-Art Verification Environment
By Cadence - 08 Jan, 2020 - Comments: 0

The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

System Electrothermal Transient Analysis of A High Current (40A) Synchronous Step Down Converter
By Cadence - 11 Dec, 2019 - Comments: 0

Authors: Rajen Murugan, Jie Chen, and Todd Harrison of Texas Instruments, Inc. and C.T. Kao and Nathan Ai of Cadence Design Systems; from Proceedings of the ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, IPACK2019, October 7-9, 2019, Anaheim, CA, USA In this paper, we detailed the system electrothermal transi... » read more

Fixed and Floating FMCW Radar Signal Processing with Tensilica DSPs
By Cadence - 04 Dec, 2019 - Comments: 0

Automotive advanced driver assistance system (ADAS) applications increasingly demand radar modules with better capability and performance. These applications require sophisticated radar processing algorithms and powerful digital signal processors (DSPs) to run them. Because these embedded systems have limited power and cost budgets, the DSP’s instruction set architecture (ISA) needs to be eff... » read more

Compressing Datasets Created During Silicon Design
By Cadence - 23 Oct, 2019 - Comments: 0

Authors: Guru Rao, Distinguished Engineer; Shakir Abbas, Software Engineering Group Director; Mohammad Mirfendereski, Configuration Management Architect; Cadence. Harsh Sharangpani, CEO and CTO; Rajesh Patil, VP-Business Development; Ascava. During the design cycle for modern semiconductor components, a very large amount of data is generated and stored, often accumulating to hundreds of tera... » read more

Celsius Thermal Solver
By Cadence - 25 Sep, 2019 - Comments: 0

The Celsius Thermal Solver environment enables all aspects of thermal analysis to quickly and accurately identify thermal problems in IC packages, PCBs, and electronics systems. It features an innovative massive parallel solver technology that enables simulation speeds up to 10 times faster than conventional thermal simulators, with significantly reduced memory usage. It includes a powerful fin... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Sep, 2019 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator
By Cadence - 26 Jun, 2019 - Comments: 0

Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

Revolution By Evolution: Getting To The Next Technology Breakthrough In Analog Simulation
By Cadence - 12 Jun, 2019 - Comments: 0

Recent technology developments, advanced-node adoptions, and Moore than Moore designs have forced analog and custom IC designers to adopt new design practices that benefit from these advancements. These changes have resulted in the need to simulate larger designs with more post-layout parasitics. In addition, many custom IC designs such as flash memory, MRAM, sensor arrays, etc., now require SP... » read more

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