Author's Latest Posts

Best Full-Flow PPA
By Cadence - 10 Jun, 2020 - Comments: 0

In the past few years, Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements such as integrated engines, massively parallel processing, and early signoff optimization, all delivering faster turnaround time and best-in-class power, performance, and area (PPA) optimization. In the era of FinFETs and ad... » read more

Computational Software
By Cadence - 03 Jun, 2020 - Comments: 0

To power the technologies and products of the future, end-application system companies are increasingly designing the full stack of their solution. Some are even designing their own semiconductors, and optimizing the end-to-end solution across chips, packages, printed circuit boards (PCBs), software, and the entire system to meet demanding market requirements. This movement is driving a converg... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 May, 2020 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis
By Cadence - 06 May, 2020 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Intelligent System Design
By Cadence - 25 Mar, 2020 - Comments: 0

Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips, and semiconductor companies are delivering software stacks, to enable substantial differentiation of their products. This trend started in mobile devices and is now moving into cloud computing, automotiv... » read more

System-Level Electro-Thermal Analysis of RDS(ON) for Power MOSFET
By Cadence - 11 Mar, 2020 - Comments: 0

Authors: Rajen Murugan1, Nathan Ai2, and C.T. Kao2 1 Texas Instruments, Inc., Dallas, Texas, 75044, USA 2 Cadence Design Systems, Santa Clara, California, USA A coupled-electro-thermal RDS(ON) (drain to source ON resistance) co-analysis methodology for Power MOSFET is proposed. The methodology contains two functional modules: 1) physical field solvers and 2) equivalent circuit/network so... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Mar, 2020 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Transient Thermal Analysis For M.2 SSD Thermal Throttling: Detailed CFD Model vs Network-Based Model
By Cadence - 15 Jan, 2020 - Comments: 0

Solid State Drive (SSD) technology continues to advance toward smaller footprints with higher bandwidth and adoption of new I/O interfaces in the PC market segment. Power performance requirements are tightening in the design process to address specific requirement along with the development of SSD technology. To meet this aggressive requirement of performance, one major issue is thermal throttl... » read more

Building A State-of-the-Art Verification Environment
By Cadence - 08 Jan, 2020 - Comments: 0

The key challenge: Build an environment with state-of-the-art verification technologies, as a model case for succeeding projects, with: • Maximum reuse of legacy IP cores and verification environments • Short turnaround time • High-quality results The customer: A global leader in microcontroller (MCU), analog, power, and system-on-chip (SoC) products, Renesas Electronics Corporation... » read more

System Electrothermal Transient Analysis of A High Current (40A) Synchronous Step Down Converter
By Cadence - 11 Dec, 2019 - Comments: 0

Authors: Rajen Murugan, Jie Chen, and Todd Harrison of Texas Instruments, Inc. and C.T. Kao and Nathan Ai of Cadence Design Systems; from Proceedings of the ASME 2019 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, IPACK2019, October 7-9, 2019, Anaheim, CA, USA In this paper, we detailed the system electrothermal transi... » read more

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