Author's Latest Posts

Enabling ISO 26262 Qualification
By Cadence - 05 Mar, 2015 - Comments: 0

ISO 26262 focuses on the functional safety of electrical and electronic systems that are installed in series production passenger cars. This adaptation of IEC 61508 is for the automotive sector and affects all systems containing software- or hardware-based electrical, electronic, or electromechanical components. ISO 26262 covers many aspects of safety-related automotive software production, i... » read more

Leveraging Physically Aware Design-For-Test To Improve Area, Power, And Timing
By Cadence - 11 Feb, 2015 - Comments: 0

Increased pressures on design teams to deliver faster, smaller devices in less time has required EDA companies to develop an integrated methodology to incorporate physical design information during DFT synthesis. This solution must consider the placeable area (or size) of the circuit as well as routing blockages and hard macro placement locations. It must also be able to both model the wiring i... » read more

Developing High-Performance, Low-Power Audio/Voice Subsystems Using Customizable DSP Blocks And Audio Interface IP
By Cadence - 14 Jan, 2015 - Comments: 0

As applications such as mobile gaming and voice triggering grow in popularity, audio/voice subsystems are becoming more important in many mobile system-on-chip (SoC) designs. Subsystem requirements have evolved to address multiple demands: high-performance, high-resolution audio stream processing, and always-on, low-power voice trigger and recognition. This white paper describes how customizabl... » read more

Enabling ISO 26262 Qualification
By Cadence - 17 Dec, 2014 - Comments: 0

This document describes how to approach the software tool qualification outlined in ISO 26262 when developing automotive electrical and electronic systems using Cadence tools. Cadence provides an ISO 26262 Tool Qualification Kit, also described in this document, that can help developers through the process with common use cases and reference workflows. Following these guidelines speeds developm... » read more

A Faster, More Accurate Approach For System-Level Performance Verification Of A Wireless RFIC Design
By Cadence - 03 Dec, 2014 - Comments: 0

Wireless RFIC designs are growing more complex, increasing the challenge of verifying system-level performance. Designers are expected to be experts on a variety of ever-changing wireless standards and protocols. They must also contend with time-consuming manual simulation setup and post-processing of the simulation results. This paper discusses how an advanced simulation methodology, involving... » read more

How To Speed Signoff Extraction By 5X With Next-Generation Extraction Tool
By Cadence - 19 Nov, 2014 - Comments: 0

Parasitic extraction, particularly in the digital world, is becoming an increasingly time-consuming process. Not surprising, considering the explosion in interconnect corners, increasing design sizes and number of parasitics, and complex modeling features at advanced nodes, including FinFETs. This paper discusses capabilities you should have in order to overcome parasitic extraction challenges,... » read more

Top 10 Ways To Automate Verification
By Cadence - 22 Oct, 2014 - Comments: 0

It’s a persistent theme: engineers are expected to do more with the same or fewer resources. Meantime, designs continue to grow larger and more complex. Studies have shown that verification continues to consume up to 70% of the IC development cost in each advanced node. Cadence’s R&D teams designed the latest version of the Incisive® functional verification platform with these pressures in... » read more

Pushing The Performance Boundaries Of ARM Cortex-M Processors For Future Embedded Design
By Cadence - 08 Oct, 2014 - Comments: 0

One of the toughest challenges in the implementation of any processors is balancing the need for the highest performance with the conflicting demands for lowest possible power and area. Inevitably, there is a tradeoff between power, performance, and area (PPA). This paper examines two unique challenges for design automation methodologies in the new ARM Cortex-M processor: How to get maximum per... » read more

Addressing Test Cost Challenges In LPCT Designs
By Cadence - 04 Aug, 2014 - Comments: 0

As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test costs down. Low Pin Count Test (LPCT) is one solution that Design for Test (DFT) designers turn to, and in many cases, might be the only one available to address these conflicting requirements. ... » read more

Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy