Addressing Test Cost Challenges In LPCT Designs

Especially in automotive and micro controllers, packages sizes are getting smaller and the number of pins being bonded out are fewer.


As companies strive to achieve higher quality and reliability for their products, and as package sizes and the number of available pins continue to shrink, there is also a persistent need to keep test costs down. Low Pin Count Test (LPCT) is one solution that Design for Test (DFT) designers turn to, and in many cases, might be the only one available to address these conflicting requirements. The overall test vector set applied during wafer and manufacturing test is often dominated by Automatic Test Pattern Generation (ATPG) patterns for digital and mixed-signal designs. Reducing ATPG test data volume and test time can significantly impact the overall test cost of these products.

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