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Machine Learning Based MBIST Area Estimation
By Cadence - 03 Jan, 2024 - Comments: 0

Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic me... » read more

System-Driven PPA For Multi-Chiplet Designs
By Cadence - 20 Dec, 2023 - Comments: 0

As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Demystifying Mixed-Signal Simulation For Digital Verification Engineers
By Cadence - 13 Dec, 2023 - Comments: 0

The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs have emerged as the dominant technology, therefore requiring traditional analog and digital methodologies to be enhanced. A mixed-signal design offers many advantages, including boosted performance, r... » read more

How The Productivity Advantages Of High-Level Synthesis Can Improve IP Design, Verification, And Reuse
By Cadence - 06 Dec, 2023 - Comments: 0

Engineering teams are under more pressure than ever before—systems on chip (SoCs) are growing more complex and design schedules are increasingly tighter. With its productivity advantages, high-level synthesis (HLS) has long been touted as part of the solution, but its sweet spot has traditionally been limited to datapath-centric blocks. Moreover, design productivity is only one part of ... » read more

Thermal Warpage Simulation Of A Temperature-Dependent Linear Elastic Material Package
By Cadence - 08 Nov, 2023 - Comments: 0

The shift to advanced packaging in 3D and 2.5D IC design is making the numerical analysis of thermal warpage in electronic devices a crucial part of the design process. A reliable numerical tool enables the designer to perform early design analysis that accurately predicts warpage, thereby shortening the design process. The Cadence Celsius Thermal Solver integrated within the Cadence IC, pac... » read more

Why A DSP Is Indispensable In The New World of AI
By Cadence - 25 Oct, 2023 - Comments: 0

Chips being designed today for the automotive, mobile handset, AI-IoT (artificial intelligence - Internet of things), and other AI applications will be fabricated in a year or two, designed into end products that will hit the market in three or more years, and then have a product lifecycle of at least five years. These chips will be used in systems with a large number and various types of senso... » read more

Unleashing The Power Of Generative AI In Chip, System, And Product Design
By Cadence - 27 Sep, 2023 - Comments: 0

The field of chip, system, and product design is a complex landscape, fraught with challenges that designers grapple with daily. The traditional design process, while robust, often falls short in addressing the increasing demands for efficiency, customization, and innovation. This white paper delves into these challenges, exploring the transformative potential of generative artificial int... » read more

Accelerating Monte Carlo Simulations For Faster Statistical Variation Analysis, Debugging, And Signoff Of Circuit Functionality
By Cadence - 23 Aug, 2023 - Comments: 0

Over the years, semiconductor process nodes have been scaled aggressively, with device dimensions now approaching below 5nm. This, along with lower device operating voltages and currents, has allowed modern integrated circuits (ICs) and system-on-chip (SoC) designs to integrate more devices in a smaller chip area without compromising on lower power consumption and optimal performance. However, ... » read more

PCIe 6.0 Electrical Testing For High Data-Bandwidth Applications
By Cadence - 19 Jul, 2023 - Comments: 0

For nearly three decades, PCI Express® (PCIe®) technology has been the standard interconnect inside computers providing high bandwidth and low latency to meet customer demand. However, as the industry needs to evolve, so does the standard, keeping pace and driving future innovation. PCIe 6.0 is ubiquitous and offers power-efficient performance and high bandwidth for latency-sensitive appli... » read more

Celsius EC Solver
By Cadence - 24 May, 2023 - Comments: 0

The Cadence Celsius EC Solver is electronics cooling simulation software for accurate and fast analysis of the thermal performance of electronic systems. It enables electronic system designers to accurately address the most challenging thermal/electronics cooling issues today. The Celsius EC Solver utilizes a powerful computational engine and meshing technology that enables designers to model a... » read more

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