A machine learning (ML)-based approach to estimate the MBIST logic area in seconds for different configurations without synthesizing the design to avoid costly design cycle iterations with an accuracy of more than 90% and help designers to choose the best possible configuration for memory testing.
Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic method of writing and reading data patterns to and from the memories. The MBIST hardware also performs the failure analysis and, when redundant resources exist, repair these memories. The number of MBIST units and their area depend upon the configuration that designers chose for memory testing based on test requirements like power, test-time, repair, programmability, algorithms and so on. With more and more functionalities being present on chip, silicon real estate is becoming crucial than ever. This puts a lot of pressure on the amount of area that can be used by MBIST unit(s). This makes it very important to estimate the area with very high accuracy to decide the configuration for memory testing. This paper describes a machine learning (ML) based approach to estimate the MBIST logic area in seconds for different configurations without synthesizing the design to avoid costly design cycle iterations with an accuracy of more than 90% and help designers to choose the best possible configuration for memory testing.
Authors: Puneet Arora, Virad Jain, Tarun Goyal, and Norman Card, all affliated with Cadence Design Systems, Austin, USA.
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