Machine Learning Based MBIST Area Estimation

By Cadence - 03 Jan, 2024 - Comments: 0

Majority of the silicon with-in a design is occupied by memories. Memories are more prone to failures than logic due to their density. Several techniques have been established to target and detect defects within these memory instances and their interfacing logic. The most widely used approach is memory built-in self-test (MBIST) that inserts on-chip hardware unit(s) which provides systematic me... » read more

Automation Of Shared Bus Memory Test With Tessent MemoryBIST

By Siemens EDA - 12 Apr, 2022 - Comments: 0

New requirements in automotive, artificial intelligence (AI), and processor applications have resulted in increased use of memory-heavy IP. Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box solution for using this single access point, or shared bus int... » read more

Automate Memory Test Through A Shared Bus Interface

By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

New Memories Add New Faults

By Bryon Moyer - 07 Sep, 2021 - Comments: 1

New non-volatile memories (NVM) bring new opportunities for changing how we use memory in systems-on-chip (SoCs), but they also add new challenges for making sure they will work as expected. These new memory types – primarily MRAM and ReRAM – rely on unique physical phenomena for storing data. That means that new test sequences and fault models may be needed before they can be released t... » read more

Convolutional Compaction-Based MRAM Fault Diagnosis

By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of mult... » read more

MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM

By Technical Paper Link - 03 Sep, 2021 - Comments: 0

Abstract: "Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is one of the most promising candidates to replace conventional embedded memory such as Static RAM and Dynamic RAM. However, due to the small on/off ratio of MRAM cells, process variations may reduce the operating margin of a chip. Reference trimming was suggested as one of the ways to reduce variation impact to the chi... » read more

Is There a Practical Test For Rowhammer Vulnerability?

By Bryon Moyer - 08 Jun, 2021 - Comments: 3

Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

Preventing Chips From Burning Up During Test

By Bryon Moyer - 09 Mar, 2021 - Comments: 1

It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

Automotive Test Moves In-System

By Bryon Moyer - 09 Feb, 2021 - Comments: 1

With the electrification of automobiles, it’s not enough to test the new electronics thoroughly at the end of the manufacturing process. Safety standards now require that tests be performed live, in the field, with contingency plans should a test fail. “We see clear demand from the automotive semiconductor supply chain for design functionality specifically aimed at in-system monitoring,�... » read more

BiST Vs. In-Circuit Sensors

By Susan Rambo - 13 May, 2020 - Comments: 0

Monitoring the health of a chip post-manufacturing, including how it is aging and performing over time, is becoming much more important as ICs make their way into safety-critical applications such as the central brain in automobiles. Faced with longer lifespans and a growing body of functional safety rules, systems vendors need to be able to predict when a part will fail. But as sensing auto... » read more

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