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CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

Everything You Need to Know about FDSOI Technology
By Coventor - 23 Jul, 2018 - Comments: 0

Over the past decades, transistor feature size has continuously decreased, leading to an increase in performance and a reduction in power consumption. Consumers have reaped the benefits, with superior electronic devices that have become increasingly useful, valuable, faster and more efficient. In recent years, as transistor feature size has shrunk below 10nm, it has become progressively more di... » read more

Understanding The Effect Of Variability In Bulk FinFET Device Performance
By Coventor - 30 May, 2018 - Comments: 0

2-D MOSFETs have proven difficult to scale down to 20nm and beyond. In their place, 3D FinFET transistors have emerged as novel devices that can scale down to lower node sizes. 10nm process finFETs are for SoC product mass production, and research is progressing towards a 7nm process finFET. FinFET transistors provide lower dynamic power consumption (due to flatter I-V curves), improved control... » read more

Modeling Semiconductor Process Variation
By Coventor - 19 Apr, 2018 - Comments: 0

3D semiconductors, 3D NAND Flash, FinFETS and other advanced devices are bringing tremendous opportunities to the semiconductor industry. Unfortunately, these devices are also bringing new design, process and production problems. Process variability has been a major contributor to production delays as feature sizes have decreased and process complexity has increased. Virtual fabrication is a co... » read more

Self-Aligned Block And Fully Self-Aligned Via For iN5 Metal 2 Self-Aligned Quadruple Patterning
By Coventor - 29 Mar, 2018 - Comments: 0

This paper assesses Self-Aligned Block (SAB) and Fully Self-Aligned Via (FSAV) approaches to patterning using a iN5 (imec node 5 nm) vehicle and Metal 2 Self-Aligned Quadruple Patterning. We analyze SAB printability in the lithography process using process optimization, and demonstrate the effect of SAB on patterning yield for a (8 M2 lines x 6 M1 lines x 6 Via) structure. We show that FSAV, co... » read more

Understanding How Small Variations In Photoresist Shape Significantly Impact Multi-Patterning Yield
By Coventor - 20 Apr, 2017 - Comments: 0

Multi-patterning schemes such as Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) have been used to successfully increase semiconductor device density, circumventing prior physical limits in pattern density. However, the number of processing steps needed in these patterning schemes can make it difficult to directly translate a lithographic mask pattern to a fin... » read more

Optimizing DRAM Development Using Directed Self-Assembly (DSA)
By Coventor - 24 Feb, 2017 - Comments: 0

Directed Self-Assembly (DSA) is an emerging technology that has the ability to substantially improve lithographic manufacturing of semiconductor devices. In DSA, copolymer materials self-assemble to form nanoscale resolution patterns on the semiconductor substrate. DSA technologies hold the promise to substantially improve the resolution of existing lithographic processes (such as self-aligned ... » read more

New Techniques To Analyze And Reduce Etch Variation
By Coventor - 25 Jan, 2017 - Comments: 1

Time division multiplex (TDM) plasma etch processes (commonly referred to as Deep Reactive ION Etching [“DRIE”]) use alternating deposition and etch steps cyclically to produce high aspect ratio structures on a silicon substrate. These etch processes have been widely applied in the manufacturing of silicon MEMS devices, and more recently in creating through silicon vias in 3D silicon struct... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D
By Coventor - 19 Oct, 2016 - Comments: 0

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

Defect Evolution In Next-Generation Extreme Ultraviolet Lithography
By Coventor - 21 Sep, 2016 - Comments: 0

Extreme ultraviolet (EUV) lithography is a promising next generation lithography technology that may succeed optical lithography at future technology nodes. EUV mask infrastructure and manufacturing of defect-free EUV mask blanks is a key near term challenge in the use of EUV lithography. Virtual fabrication is a computerized technique to perform predictive, three dimensional modeling of sem... » read more

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