How to model the impact of DSA techniques into a full semiconductor process flow.
Directed Self-Assembly (DSA) is an emerging technology that has the ability to substantially improve lithographic manufacturing of semiconductor devices. In DSA, copolymer materials self-assemble to form nanoscale resolution patterns on the semiconductor substrate. DSA technologies hold the promise to substantially improve the resolution of existing lithographic processes (such as self-aligned quadruple patterning, or SAQP), leading to higher density semiconductor devices.
Virtual fabrication is a computerized technique to perform predictive, three-dimensional modeling of semiconductor fabrication processes. Virtual fabrication allows engineers to test semiconductor process changes and process variability in minutes or hours, instead of the weeks or months required to test their designs using actual semiconductor wafers. SEMulator3D is a virtual fabrication solution that can model process variability under complex patterning schemes and process flows.
SEMulator3D can be used to model the impact of integrating directed self-assembly (DSA) techniques into a full semiconductor process flow. In this study, SEMulator3D was used to analyze the incorporation of advanced DSA patterning processes into the fabrication of a 14nm DRAM array.
To read more, click here.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
New market opportunities and global competitiveness are limited by qualified people.
Researchers digging into ways around the von Neumann bottleneck.
The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.
Better algorithms and more data could bolster adoption, particularly at advanced nodes.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
New architectures, packaging approaches gain ground as costs increase, but shrinking features continues to play a role.
Improvement still needed for uptime, defectivity, line edge roughness and process flows.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply