Author's Latest Posts


How Chip Engineers Plan To Use AI


Experts at the Table: Semiconductor Engineering sat down to discuss how AI is being used today and how engineers expect to use it in the future, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta; and David Pan, professor in the ... » read more

How Curvilinear Mask Writing Affects Chip Design


As chips become more complex and features continue to shrink, it becomes more difficult to print shapes on photomasks. The ability to print curvilinear masks changes that equation, but not all of the pieces in the flow are automated today. Aki Fujimura, CEO of D2S, talks about what has to change, what will the impact be on design rules, and why using curvilinear shapes can shrink the manufactur... » read more

What’s Required To Secure Chips


Experts at the Table: Semiconductor Engineering sat down to talk about how to verify that a semiconductor design will be secure, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketing at Expedera; and Dave Kelf, CEO of Breker Verification. ... » read more

Adding Security Into Test


Security is becoming a much bigger concern as more electronics are added into cars, as more devices are connected to the internet, and as the value of data continues to increase. The problem is that security is dynamic. It continues to change throughout the lifetime of a system, and some of these devices are expected to last for a decade or more. Lee Harrison, director of Tessent product market... » read more

Mechanical Challenges Rise With Heterogeneous Integration


Companies integrating multiple chips or chiplets into a package will need to address structural and other mechanical engineering issues, but gaps in the design tools, new materials and interconnect technologies, and a shortage of expertise are making it difficult to address those issues. Throughout most of the history of the semiconductors, few people outside of foundries worried about struc... » read more

Impact Of Increased IC Performance On Memory


Increasing performance in advanced semiconductors is becoming more difficult as chips become more complex. There are more physical effects to contend with, different use cases, and challenges in making memory go faster. In addition, aging effects that once were ignored are now becoming critical concerns. Steven Woo, fellow and distinguished inventor at Rambus, talks about different factors that... » read more

AI Becoming More Prominent In Chip Design


Semiconductor Engineering sat down to talk about the role of AI in managing data and improving designs, and its growing role in pathfinding and preventing silent data corruption, with Michael Jackson, corporate vice president for R&D at Cadence; Joel Sumner, vice president of semiconductor and electronics engineering at National Instruments; Grace Yu, product and engineering manager at Meta... » read more

Mini-Consortia Forming Around Chiplets


Mini-consortia for chiplets are sprouting up across the industry, driven by demands for increasing customization in tight market windows and fueled by combinations of hardened IP that have been proven in silicon. These loosely aligned partnerships are working to develop LEGO-like integration models for highly specific applications and end markets. But they all are starting small, because it'... » read more

MIPI’s Focus Widens


Ashraf Takla, president and CEO of Mixel, sat down with Semiconductor Engineering to talk about the evolution of MIPI, from mobile displays to automotive, chiplets, and how the standard is evolving to keep up with increasing data volumes. SE: There has been a lot of activity around MIPI in automotive. What's driving that? Takla: One of the early use-cases for MIPI, after Mobile has been ... » read more

Physically Aware NoCs


More functions, greater security risks, and increasingly complicated integration of IP and various components below 7nm is increasing the time and effort it takes to get a functioning chip out the door. In many of these devices, the network on chip is the glue between various components, but it can take up to 10% to 12% of the total area of the SoC. Andy Nightingale, vice president of product m... » read more

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