Mechanical Challenges Rise With Heterogeneous Integration

But gaps in tools make it difficult to address warpage, structural issues, and new materials in multi-die/multi-chiplet designs.


Companies integrating multiple chips or chiplets into a package will need to address structural and other mechanical engineering issues, but gaps in the design tools, new materials and interconnect technologies, and a shortage of expertise are making it difficult to address those issues.

Throughout most of the history of the semiconductors, few people outside of foundries worried about structural issues. A silicon substrate could easily support any of the films deposited on top or etched away. But as SoCs are disaggregated into smaller chips, and as hardened IP blocks are combined in the form of chiplets, different use cases add unexpected stresses that can affect reliability. Among the causes:

  • Organic interposers are being introduced for both cost and size reasons — they can be customized to any size — but they are much more flexible than silicon interposers, which increases the likelihood of warpage if they are not handled or packaged properly.
  • Chips or chiplets increasingly are being stacked on top of each other, which adds mechanical stresses. Those stresses often are exacerbated by heat, which can cause thermal mismatches between chiplets, interconnects, and various types of fill and bonding materials. While some of this can be accounted for up front, it also can vary significantly by use case.
  • At advanced nodes, substrates are being thinned to shorten distances signals must travel and to reduce resistance and capacitance. Meanwhile, thousands of holes are being drilled into those substrates for through-silicon vias and backside power delivery, which can cause micro-cracking that goes undetected during manufacturing. As these devices are stressed in other ways, that cracking can spread.

MIT Technology Review Insights just released a report, commissioned by Synopsys, that polled 302 executives across more than a dozen industries. It found that 38% were at least aware and exploring multi-die chip designs as the way to generate enough horsepower to tackle future computing needs. The report also pointed out some of the challenges that need to be solved.

“You’re dealing with physics when you have to connect between chips,” said Gerry Talbot, corporate fellow at AMD in the report. “The physical size of components, interconnect, layer transitions, the size of the package—all of these things limit you from being able to scale the bandwidth of the interface between chiplets.”

The situation is far more acute for most other companies. AMD uses internally developed chiplets. But with chiplets from multiple foundries and vendors, many more interactions are possible.”With multi-die, there are still many complications,” said Sassine Ghazi, president and COO of Synopsys. “How do you disaggregate your architecture and do this what-if architectural analysis all the way through the thermal, the stress, the reliability? Nobody offers that today. “It’s still a very manual effort. The architect needs to decide, ‘Where is my processor, where is my accelerator, my memory? How do I put in my bus?’ Once you do that and have disaggregated your chip, the analysis portion of the thermal, reliability, timing, power, etc., between the dies is there. But that first stage is still manual.”

Organic interposers add another challenge. “Warpage is one of our key concerns,” said Ingu Yin Chang, senior vice president at ASE Group. “As we assemble multiple chips — sometimes 7 to 12 chips on a single organic substrate — that’s one of the key mechanical challenges we face today. This stretches across a very large format we typically don’t look at in the assembly world, but now we have to look at it. This could be a 150 x 150 substrate, and that becomes a bigger challenge for us.”

Even if the warpage is effectively addressed during assembly and packaging, a device (or some segment of it) still may warp under heavy usage in the field. This is particularly true with heterogeneous designs, where the chiplets are developed using different materials or processes, and where logic is concentrated in one or more areas of a package. As those areas expand and contract, or various parts of a package heat up more than others, stress increases on the interconnects and bonds between the different components and the substrate or interposer.

“The current going through these bumps assumes a certain resistance,” said Marc Swinnen, director of product marketing Ansys. “But if you have a failure in one of these bumped connections, where you have a narrow connection bridge, you’re putting a lot of power through that little bridge. It gets hot, and that causes it to melt. We’ve seen simulations from customers where if it melts down, the other bumps get more current, and those will melt, and so you have a cascading thermal failure. You can’t predict which bump or how many bumps will fail, so you have to look at, ‘If two or three bumps fail, in what pattern will they cause the maximum damage?’ You need to have enough spare conduction resource to carry the power to all these bumps, and that’s your thermal analysis and current analysis.”

Those issues become even more pronounced with hybrid bonding. “Bumps are like big shock absorbers,” said Nir Sever, senior director of business development at proteanTecs. “Micro-bumps are like small shock absorbers. But a hybrid bond has no shock absorber whatsoever. There is no excess material to compensate for that. Problems are going to show up even if you think you have tested for all of them and the chip is deployed and running data. It’s heating, cooling, and starting to deform, and even the slightest defect that was undetected at time zero can eventually cause a single line to fail and produce an error. This is one cause of silent data corruption. On top of that, other issues may manifest in the field, like degradation and accelerated aging. So it’s crucial to continue monitoring the chip throughout its lifetime.”

Chiplets require many more connections than other approaches. “In packaging we’re used to dealing with a few thousand connections for signals, and a lot more than that for power and ground, so there may be less than 50,000 connections,” said John Park, product management group director for IC packaging and cross-platform solutions at Cadence. “But now with chiplets, you could be facing 100,000 plus connections, which means an auto-router is needed to handle that kind of capacity.”

Fig. 1: Options for heterogeneous integration over time. Source: Cadence

Different coefficients of thermal expansion add another potential source of mechanical stress, a problem that gets worse if chiplets are different sizes, and especially when they are stacked vertically.

“If you bond die that are different sizes and pre-tested, you need to fill in that space caused by the mismatch of die sizes with something,” said Javier DeLaCruz, fellow and senior director of silicon operations engineering at Arm. “But almost everything you’re going to add in there will have poor thermal conductivity. So you will have bigger thermal gradients across those regions, and anytime you have a thermal gradient you have additional stress. If you have a change in conductor metal, then electromigration comes into play. It’s the filler material that’s the new element. Traditionally, we’ve always had to worry about the mismatch between silicon and a package substrate with interposers. But in 3D, you need to worry about silicon-to-silicon stress with the introduction of that filler material, whether it’s mold compound or oxide or whatever else it is, that’s going to have a different coefficient of thermal expansion than what the rest of the silicon has.”

All of this needs to be taken into consideration very early in the design process. Alternatively, performance needs to be throttled back when a certain temperature is reached in critical components so the device doesn’t burn up.

“It depends on the amount of power involved and how the heat is handled,” said Nathan Whitchurch, senior staff engineer at Amkor. “If you don’t have a heat sink and you’re pushing all the heat down through the board, that matters. If you’re pushing all the heat out the top through a heat sink or some cold plate design, you fundamentally haven’t changed any of the components in the heat path, whether you’re using 2.5D or a 40-layer or 2-layer substrate.”

Chiplets vs. soft IP
Most of the IP used in semiconductors today is soft IP. It typically is process-independent, or at least process-resilient. Hardening that IP into chiplets changes that relationship.

“Hardening IP requires experience and could be a challenge,” said Arm’s DeLaCruz. “There’s a whole other competency required for handling silicon — yield, storage, material handling, ownership of yield problems when it gets integrated into systems. These can all be messy items if they’re not really well planned out.”

All of those elements play a role in the type of package chosen, and when that choice needs to be made in the design-through-manufacturing flow.

“We have to get involved much earlier in the design stage. In the past, you almost finished your layout and then asked, ‘What do we do about packaging?’ said ASE’s Chang. “Designs are more comprehensive now, because the mechanical stresses need to be considered simultaneously with the rest of the design. So now not only are you designing your transistor or core IPs, but you have to look at what type of floor plan you’re going to have in terms of chiplet layout.”

In effect, what used to be described as “shift left” is becoming a stack of concurrent processes, and the data required at each step needs to be much more comprehensive.

“IP companies are going to have to evolve because of the level of analysis and information they will need to provide to push forward,” said Michael Munsey, senior director of technology solutions sales at Siemens Digital Industries Software. “If you’re a smaller IP company that is doing piece parts, like a USB or PCI, that’s going to go into something larger. But you’re going to see IP companies coming out with chiplets, and those are really going to need information that will feed not only into the electrical analysis, but also the mechanical analysis, to produce an integrated flow.”

Compute density is only increasing, as well, and putting all of these different compute elements into a package makes it more difficult to dissipate the heat. That, in turn, can cause mechanical stress elsewhere in a heterogeneous device, but not always where one would expect it to happen.

“If you have AI accelerators, and it has 1 killowatt of power in the package, then you have so much heat in the system and so much mechanical stress from warming up of systems that you have to consider that,” said Andy Heinig, head of department for efficient electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “We need more standards. Maybe we also need standards for mechanical interfaces to realize the chiplet ecosystem. We definitely see some gaps. But first we need prototypes demonstrated, bringing together chiplets from different partners, so we can see what is missing. The chiplet ecosystem is totally different from what we have seen on the Intel and AMD side, where they do everything in-house and have everything under control. If we really want to build an open ecosystem, then we will see a lot of problems pop up in the future.”

Thermal and mechanical are not entirely independent. “Pressure generates heat,” said John Ferguson, director of product management for Calibre nmDRC at Siemens EDA. ”  As such, the more stacking applied, the higher the at-rest temperature.  Similarly, as materials are heated they expand.  Given a system made up of several different kinds of materials, each with different thermal coefficients, exposure to periodic heating and cooling ultimately leads to reliability issues such as EMIR impacts.”

Accounting for all of  this adds to the design cost, as well, which may limit how companies approach multi-die integration.

“If we’re getting multiple die from multiple places, the first thing you have to look at if these things are already built is what pin pitch they are at,” said Cadence’s Park. “For example, in a die-to-die chiplet based on UCIe, there is an option for standard packaging, which would be something like a flip chip with 125- or 130-micron pin pitch versus something that would go on an interposer that could be down to a 35-micron pitch. If the pin pitch is down to 40 or 50 microns, I have to either use a silicon interposer or some sort of interconnect bridge to do that, which increases the cost. And that’s why some may choose a standard package version, because if you put everything at a flip chip pitch of 125-micron, you can do that on a traditional laminate package, which is significantly less cost than using a silicon interposer or embedded bridge.”

And that cost could rise significantly if the device fails prematurely. “If you are a company that assembles chiplets from multiple vendors, and you have the interconnect done, you still have to integrate and take responsibility for the testing of that system,” said proteanTecs’ Sever. “For example, if you have four partners, you’re getting separate test programs from each of them with their own test methodology. As the chiplet integrator, you’re responsible for testing the final product, and when there’s something wrong, you need to know why. When a monolithic chip is failing, it’s your own die and you have the necessary information to debug. But if you have four different providers, how do you know which one is responsible? The chip that detected the error is not necessarily the root cause of the problem, because it may be fed bad data from another chip provider that is upstream in the data chain.”

Customization adds another level of complexity when it comes to stress. While a custom design, in theory, can provide maximum energy efficiency and performance, it also brings together a lot of pieces in unique ways. There has been some discussion at various conferences about whether the first commercial chiplets will be subsystems rather than individual chips with very specific functions.

“A standard interface that does the same thing as everyone else does isn’t going to differentiate your product,” said Michael Posner, product line senior group director for IP at Synopsys. “If you want to squeeze a little more performance out, or lower you power, or differentiate across the interface, that’s why we customize IP. But with these packaging technologies, it’s becoming harder to do that. UCIe is defined for standard or organic interposer-based or silicon bridge. So immediately you have to sacrifice the bump pitches. Even with standard UCIe-defined 100nm bump pitch, that’s not auto-grade tested yet, but 130nm on organic is automotive grade. So you’ve got this interim area where there’s a mismatch between the standards and the technology. And then you’ve got mechanical issues, where there isn’t enough data yet to really do a lot of simulations — and even those are based on some theoretical. We need a lot more data.”

As with all new approaches, many ideas are being floated. Which ones stick remains to be seen.

“Moving forward, thermal analysis information could be stored as metadata on the chip itself, and then passed into the mechanical/thermal analysis tools to do that level of analysis,” said Siemens’ Munsey. “And when you get into that electrical/mechanical/system-level analysis, you’re going to collect a lot of really useful data that could be fed back into the flow. So we hear things about shift left and trying to shift left that actually starts with mechanical information to drive decision-making earlier in the process and for next-generation products.”

This applies to chiplets as well as to non-chiplet designs. “Consider how power is optimized in traditional place-and-route today,” said Ferguson. “For each block there is a specified level of expected power requirements. This helps to drive placements to meet the overall power utilization constraints at the chip level. The same will need to be done for chiplets in a 3D-IC environment.  This implies performing electro-thermo-mechanical analysis on each chiplet in a minimal package to capture the tolerances to electrical behavior within a given thermo-mechanical window, along with corresponding standards for how such information is stored and transferred.  From there, as each chiplet is placed into a larger 3D-IC encapsulation, subsequent thermo-mechanical analysis is needed to identify if the configuration meets the minimal spec for each chiplet placement in the assembly. Of course, automation will still remain something of a challenge given the performance and capacity requirements for thermos-mechanical simulations with the current state-of-the-arts solutions.”

It’s not entirely clear how chiplets will roll out, or how they will be packaged. But there is a clear direction toward heterogeneous integration in advanced packages, and a lot of problems that have at least been identified, even if there currently is no solution.

“More-than-Moore is the only way to go forward with electronics. There may be 2nm or 1nm designs, but the number of designs at those technology nodes will be very limited because of the cost,” said Fraunhofer’s Heinig. “But right now nobody wants to be the first to build a system out of chiplets from different vendors. They don’t want to have to spend millions of dollars to take the risk and to understand the whole supply chain, what is necessary, and to develop the first prototypes to show everybody how it can work and what may be the blocking points. They’d rather be second.”

Related Reading
Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
EBook: Chiplets may be the semiconductor industry’s hardest challenge yet, but they are the best path forward.

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