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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.

Author's Latest Posts

10 Questions: Handel Jones
By Ed Sperling - 20 Sep, 2022 - Comments: 0

Handel Jones, CEO of International Business Strategies and author of a new book, "When AI Rules The World," sat down with Semiconductor Engineering to talk about the growth and impact of AI. What follows are excerpts of that conversation. SE: What do you see as the impact of AI on semiconductors? Jones: The fact that you have a 5G smart phone is because of AI. Steve Jobs changed the smart... » read more

How To Compare Chips
By Ed Sperling - 15 Sep, 2022 - Comments: 0

Traditional metrics for semiconductors are becoming much less meaningful in the most advanced designs. The number of transistors packed into a square centimeter only matters if they can be utilized, and performance per watt is irrelevant if sufficient power cannot be delivered to all of the transistors. The consensus across the chip industry is that the cost per transistor is rising at each ... » read more

Quantum Computing
By Ed Sperling - 12 Sep, 2022 - Comments: 0

Sebastian Luber, senior director of technology and innovation at Infineon Technologies, talks about the growing interest in quantum computers, what’s still missing to make this technology more relevant, and how to improve the lifespan and accuracy of qubits. » read more

Quantum Research Bits: Sept. 12
By Ed Sperling - 12 Sep, 2022 - Comments: 1

Making Qubits Last Longer One of the big challenges in quantum computing is extending the lifespan of qubits, called coherence time, long enough to do something useful with them. Research is now focused on how to increase that usable lifetime, and what factors can impact that. This has led to very different conclusions about whether silicon is a good substrate choice for quantum chips. Rese... » read more

Making 5G More Reliable
By Ed Sperling - 08 Sep, 2022 - Comments: 0

The rollout of 5G is a complex and monumental effort involving multiple separate systems that need to function flawlessly together in real-time, making it difficult to determine where problems might arise, or how and when to test for them. Investments in 5G have been underway for the better part of a decade, and the technology is considered the next huge growth opportunity for mobile devices... » read more

Boosting Data Management System Performance
By Ed Sperling - 07 Sep, 2022 - Comments: 0

Marios Karatzias, application engineer at ClioSoft, talks with Semiconductor Engineering about the increasing use and re-use of IP in designs, how to best keep track of that IP, and how to optimize the performance of the data management system to deal with IP in heterogeneous chips. This is particularly important in automotive and industrial applications, where a specific version of IP may have... » read more

Big Changes In Architectures, Transistors, Materials
By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

A Sputnik Moment For Chips
By Ed Sperling - 02 Aug, 2022 - Comments: 5

Chip shortages are the new Sputnik moment, and they have created a sense of national and regional panic not seen since the days of the Cold War. For both the United States and Europe, those shortages have sparked some of the largest technology investments by government in the past half-century that are not strictly for the military — and by far the biggest involving semiconductors. Whi... » read more

Scaling, Advanced Packaging, Or Both
By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

Customization, Heterogenous Integration, And Brute Force Verification
By Ed Sperling - 14 Jul, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

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