Frank Schirrmeister

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Frank Schirrmeister is executive director, strategic programs, system solutions in Synopsys' System Design Group. He leads strategic activities across system software and hardware assisted development for industries like automotive, data center and 5G/6G communications, as well as for horizontals like AI/ML. Prior to Synopsys, Schirrmeister held various senior leadership positions at Arteris, Cadence Design Systems, Imperas, Chipvision and SICAN Microelectronics, focusing on product marketing and management, solutions, strategic ecosystem partner initiatives, and customer engagement. He holds an MSEE from the Technical University of Berlin and actively participates in cross-industry initiatives as chair of the Design Automation Conference's Engineering Tracks.

Author's Latest Posts

DAC 2018: System Design, Cloud And Machine Learning
By Frank Schirrmeister - 28 Jun, 2018 - Comments: 0

This marks the 10th DAC that I have covered as a blogger. At DAC 2008 in Anaheim, the industry had just come together behind the SystemC TLM 2.0 standard to enable virtual platforms, finally getting to model interoperability. System design is the common thread that is also present in this year’s DAC in 2018 in San Francisco. But a lot has changed. Big data analytics, artificial intelligence a... » read more

Electronic System-Level Design: Are We There Yet?
By Frank Schirrmeister - 24 May, 2018 - Comments: 0

I am writing this while attending NI Week in Austin and am admittedly wowed by National Instruments’ open test platform. NI Week’s theme is “Developing the Future Faster.” The Tuesday keynote included guest speakers from Mazda, Honeywell, and NXP, and these were great examples of system-level design of different scopes, from cars to distributed systems to chips enabling them. Personally... » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018
By Frank Schirrmeister - 26 Apr, 2018 - Comments: 0

Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

Embedded World 2018: Security, Safety, And Digital Twins
By Frank Schirrmeister - 22 Mar, 2018 - Comments: 0

This year's embedded world in Nuremberg was again very well attended despite a cold wave in Europe. The key trends I had expected to see were safety and security, and the exhibits did not disappoint. One additional key theme that stood out to me was that of “digital twinning.” And, of course, the battle of processor ecosystems does continue. RISC-V has joined the games and feels a bit like ... » read more

AI And Machine Learning Drive New SoC Verification Choices
By Frank Schirrmeister - 22 Feb, 2018 - Comments: 0

I have previously written about the choices that design teams have when choosing specific verification engines—virtual, formal, simulation, emulation, FPGA and actual silicon. As a new class of SoC is emerging for machine learning and artificial intelligence with complexities previously unheard of, they further deepen the challenge of choosing the right tool for the job. Even the choice betwe... » read more

It Takes A Village… To Develop And Verify SoCs
By Frank Schirrmeister - 25 Jan, 2018 - Comments: 0

In my last blog post from 2017, “Design Chains Will Drive The Top 5 EDA Trends In 2018,” I had pointed to the importance of ecosystems for electronics development in general. From an EDA perspective, it also takes a village to shepherd the actual chip development with its complex verification and software development tasks. And the types of partnerships often depend on the application domai... » read more

Design Chains Will Drive The Top 5 EDA Trends In 2018
By Frank Schirrmeister - 21 Dec, 2017 - Comments: 0

In my prediction piece last year, I made seven trend predictions. Looking back, I did very well compared to what actually happened. For 2018, I am cutting it down to five trends that will impact EDA, but in my mind a lot of the trends will be driven by the ever-evolving ecosystem of design chains from IP though semiconductor to systems and to OEMs. While HBO’s 'Game of Thrones' comes to a con... » read more

5 Pitfalls That May Kill The IoT
By Frank Schirrmeister - 30 Nov, 2017 - Comments: 0

A couple of weeks ago I participated in a panel titled “The Road to a Trillion Devices” organized by Brian Fuller at Arm TechCon. His closing question was whether we will get to the projected trillion devices in twenty years. My answer was that we may even get there faster. His opening question was what the pitfalls would be to make it difficult to get to trillion devices in the next twenty... » read more

Use Model Versatility: Key To Return On Investment For Emulation
By Frank Schirrmeister - 26 Oct, 2017 - Comments: 0

When we announced Palladium Z1 now almost two years ago in November 2015, we emphasized versatility of use models as a key component to optimize return on investment when adopting emulation. Today, our biggest customers are using emulation as a compute resource with 10s of projects in parallel, and they are running a large number of different use models on it. This year alone, more than 30 cust... » read more

System Design And Verification Challenges: Are They On- Or Off-Chip?
By Frank Schirrmeister - 28 Sep, 2017 - Comments: 0

What are the next natural items for mobile devices to be integrated? From 2002 to today, previously separate items (like GPS, cameras and keyboards) have been integrated into the phone. They caused a frenzy of integration within systems on chips. Now we have the Internet of Things (IoT) adding a trillion devices to the picture. Which ones are to be integrated, if any? What does all this mean fo... » read more

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