Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018

Tradeoffs can be a good thing when you have the flexibility to choose what’s important.


Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, and test and options for prototyping.

At our booth, we were showing our Palladium Z1 emulator—always a great draw for conversations—and for the first time ever two Protium S1 demos were shown side by side. One demonstrated a manually optimized FPGA-based prototype that takes longer to bring up and is faster, the other demonstrated the same design as an “out of the box” FPGA-based prototype brought up in days using automation.

One hardware. A range of use models.

The picture illustrates two versions of a Tensilica P6-based pedestrian recognition system as it would be used in ADAS automotive applications. In classic FPGA-based prototyping, a bring-up from scratch typically takes months. RTL needs to be modified, memories need to be remodeled, clocks need to be synchronized manually, and after all modifications, users need to verify that the resulting prototype still has the same functionality as the original RTL.

In contrast, the Protium S1 automated flow takes care of all of this, getting to a working prototype fast. This is shown on the right-hand side. Designs come up within days or a small number of weeks, and users get a run-time GUI and debug facilities. Especially of a design run in Palladium before, we use the same database and the bring-up in FPGA is very fast. Nothing comes for free, though—in doing this, the resulting performance of a prototype is a bit slower—we see 3MHz to 10MHz out of the box, depending on design size. For many users, that speed is sufficient to start with.

Now, while the software developers are already off being productive bringing up operating systems and developing drivers and middleware, the optimization of the prototype can continue. Interfaces like PCIe can be black-boxed, and critical components can be optimized manually using FPGA vendor tools like Xilinx’s Vivado. This is shown on the left-hand side. The design has been optimized further and now runs even faster, getting to about twice the frame rate as the automatically brought up prototype, in our case.

This is a unique capability that users appreciate—they get the flexibility to choose between fast bring-up and manually optimized speed, all on the same platform.

Our systems track at CDNLive as always was focused on full SoCs, specifically their verification and software development methods, and it includes the hardware accelerated technologies.

FPGA-based prototyping was big this year, and in the spirit of above description, NVIDIA’s presentation title said it all: “Pushbutton Prototyping in Days vs. Months.” They brought up multiple GPU and SoC designs consistently in days compared to weeks/months, at 10X to 20X speed over the equivalent emulation model. Microsemi’s “Pre-Silicon Software/Firmware Testing with Protium S1 Platform: A Case Study” won the best paper award, and focused on what can be done with Protium S1 without even having access to Palladium Z1 as a companion. They were able to boot uBoot and Linux, download firmware, debug software with ARM DSTEAM probe and use ARM CoreSight for software traces and CPU profiling. They also found RTL bugs and were very successful with all major data paths up and running with software. Another group from Microsemi presented on “Palladium Z1 and Protium S1: The Fastest Way to Make Your System-on-Chip Prototyping a Success Story.” The presentation showed the full flow of all engines and the illustration of the complex unified ecosystem of Protium S1 and Palladium Z1.

Virtualization is an important topic. MicroSemi’s “Bringup and Debug Challenges of a 16X Arm Core System, Running Embedded Firmware in a UVM TB” illustrated a great case study why virtualization is an important addition to physical connections. Our VirtualBridges and Accelerated VIP helped to achieve 200X acceleration.

Development ecosystems are crucial in EDA and we had made this one focus are of the systems track. My joint presentation with National Instruments, called “Towards Systems of Systems Verification – Connecting Design and Test” focused on the ecosystem of Palladium and Protium, and how to connect verification with external test and lab equipment. The highlight was a demo on how to connect a UVM testbench to an external hardware design under test. In “Pioneering High-Performance and High-Fidelity Ethernet Switch Verification for the Networking Market,” Ixia outlined our great partnership, including details of advantages of the different options that users have and showing how testing in networking can be done using physical, semi-virtual and virtual solutions. Samsung’s “Maximizing ROI of Palladium Platform While Efficiently Managing Big Data Complexity Associated with Emulation Jobs” was a great case study how the infrastructure can contribute significantly to the overall performance and user experience in emulation. Very practical and applicable to the day-to-day life of emulation teams. Security is a big issue across all application domains these days. Tortuga Logic’s “Enabling Full Design Lifecycle Hardware/Software Security Verification” was a great case study closing the track, emphasizing how Cadence partners with Tortuga to run their security IP in Xcelium simulation and Palladium emulation.

Finally, a frequently-mentioned topic in system design is the area of portable stimulus and tracking of metrics and requirements; Arm, TVS, and NXP presented here. In “Integration and Verification of PCI Express Gen4 Root Complex IP into an Arm-Based Server SoC Application” Arm emphasized how portable stimulus provides a huge productivity boost with out-of-the-box functionality for Arm and PCIe libraries, and how the portable tests run on simulation, emulation, and FPGA. In “Delivering on the Promises of Portable Stimulus,” TVS’s CEO Mike Bartley gave a good introduction to the topic underlining the interesting dynamic between the language options that users have. And NXP’s “Integration of vManager Platform with Industry-Standard “DOORsNG” to Address Requirement Traceability” showed the importance of planning and linkage back to requirements for the product development.

This must have been the most interesting CDNLive I have been at so far. System Development is a lively topic! If you want to review any of the presentations, please go to the Cadence CDNLive events page.

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