Week In Review: Design, Low Power


M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

Week In Review: Design, Low Power


ANSYS acquired the assets of DfR Solutions, a developer of automated design reliability analysis software. Founded in 2004 and based in Maryland, DfR's tool translates ECAD and MCAE data into 3D finite element models, automates thermal derating and performs thermal and mechanical analysis of electronics earlier in the design cycle. "ANSYS brings industry-leading electronic simulation capabiliti... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs


Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Partitioning Becomes More Difficult


The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018


Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

Can Big Data Help Coverage Closure?


Semiconductor designs are a combination of very large numbers and very small numbers. There is a large numbers of transistors at very small sizes, and databases are often large. The chip industry has been looking at [getkc id="305" kc_name="machine learning"] to effectively manage some of this data, but so far datasets have not been properly tagged across the industry and there is a reluctan... » read more

Merging Verification With Validation


Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

The Week In Review: Design


Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

Which Verification Engine?


Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

The Trouble With Models


Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

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