Confusion Persists In Verification Terms


I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am talking about verification terminology. I have been in this industry for over 40 years and it is not improving. In fact, it is getting worse. The number of calls I have with people where they hav... » read more

The Evolution Of Digital Twins


Digital twins are starting to make inroads earlier in the chip design flow, allowing design teams to develop more effective models. But they also are adding new challenges in maintaining those models throughout a chip's lifecycle. Until a couple of years ago, few people in the semiconductor industry had even heard the term "digital twin." Then, suddenly, it was everywhere, causing confusion ... » read more

Universal Verification Methodology Running Out Of Steam


For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, more complex, and significantly larger, UVM is running out of steam. Consensus is building that some fundamental changes are required, moving tools up a level of abstraction and making them more ag... » read more

Open-Source Verification


Ask different people what open-source verification means and you will get a host of different answers. They range from the verification of open-source hardware, to providing an open-source verification infrastructure, to providing open-source stream generators or reference models, to open-source simulators and formal verification engines. Verification is about reducing risk. "Verification is... » read more

The Meaning Of Verification


When I ask the question "Why do we do verification?" there are generally two types of responses. One of them sees the glass as half empty and the other as half full. It depends upon how you look at the problem and if you see verification as being a positive or negative operation. The negative answer is that we do verification to find bugs. This relies on the mechanical function of creating v... » read more

Will Open-Source Processors Cause A Verification Shift?


While the promised flexibility of open source could have advantages and possibilities for processors and SoCs, where does the industry stand on verification approaches and methodologies from here? Single-source ISAs of the past relied on general industry verification technologies and methodologies, but open-source ISA-based processor users and adopters will need to review the verification flows... » read more

The Challenge Of Defining Worst Case


Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive — startups and systems companies are now competing with established chipmakers — no one can afford to consider theoretical worst cases. Instead, they must intelligently prune the space to make sur... » read more

Which Verification Engine When


Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Rapid Evolution For Verification Plans


Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Abstract Verification


Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become an accepted and trusted methodology. This becomes particularly true when we bring abstraction into the picture. A virtual prototype is meant to be true to behavior, but there could be timing d... » read more

← Older posts