Use Model Versatility: Key To Return On Investment For Emulation

When we announced Palladium Z1 now almost two years ago in November 2015, we emphasized versatility of use models as a key component to optimize return on investment when adopting emulation. Today, our biggest customers are using emulation as a compute resource with 10s of projects in parallel, and they are running a large number of different use models on it. This year alone, more than 30 customer experience about Palladium Emulation have been presented at user conferences across a least 15 different use models. As we are marching towards the end of 2017 here, emulation truly has become a compute resource in the data center.

Thinking about pure access to emulation, a key capability is data center readiness. Emulation users expect data center density and connectivity with a rack-based footprint, high speed optical interfaces and the ability to expand hosts – Palladium Z1 offers 56Gbs optical and Infiiniband Switches for expandability. To optimize availability and utilization of an emulation platform, diverse payloads of different sizes and lengths have to be executed with as little interruption as possible. Palladium Z1 for instance offers power module redundancy as they are hot-swappable and it is still the only emulation system that offers fine-grained user granularity of 4MG increments for design sizes scaling from 4M to 9.2BG, enabling overall 10 to 15x better utilization than the nearest competing platforms. Palladium Z1 is datacenter and cloud ready, easing adoption with advanced job allocation and virtualization features.

Figure 1 – Emulation Use Models in Palladium Z1

With respect to use model versatility and scalability, Palladium Z1 offers 22+ use models for RTL and gate-level netlist with unparalleled debug including capabilities like “FullVision”, “InfiniTrace”, “Virtual Verification Machine”, “Dynamic Probes” and “SDL based triggering.” The number of Palladium applications is constantly growing, advancing SpeedBridge interfaces for in-circuit emulation, Accelerated Verification IP with transactors for most popular interfaces to allow acceleration, pre-assembled Emulation Development Kits, advances in Dynamic Power Analysis by vertically integrating with RTL power estimation like Joules and Virtual Emulation and Virtual Debug.

With only 66 days left in the year, we have 8 of our 9 worldwide CDNLive user conferences already behind us, as well as the main EDA conferences like DVCON, Embedded World, DAC and DATE. Looking back, it is fascinating to see all the user experiences as they document the importance of use model versatility.

Early in the year Samsung presented at DVCON 2017 in San Jose on low power optimization using Palladium emulation in a presentation titled “Emulation-Based Full-Chip-Level Low-Power Validation at Pre-Silicon Stage,” showing how they apply early power optimization in Palladium to their application processor development, getting as close as 1.8% in accuracy compared to the actual silicon. This also involves software as the speed of emulation makes it feasible to run real software payloads.

At Embedded World and CDNLive San Jose we co-presented with ARM on HW/SW Debug with their debug tools, as well as on Hybrid emulation that combines virtual platforms with emulation, achieving up to 50x faster OS Boot and software bring-up. CDNLive San Jose also featured Netronome on software driven verification, saving them many person months by running trillions of real packets, Amlogic on Pre-Silicon Software Development with Protium/Palladium, enabling full Android demos to their customers 3 days after silicon availability, NVIDIA on Virtual Emulation and the complementary use of SpeedBridges and VirtualBridges, MicroSemi on Verification Acceleration, achieving 40x speed-up, NVIDIA on Hybrid Emulation enabling earlier availability and faster time to completion of the validation plan, and Marvell on how to balance usage of emulation and FPGA based prototyping.

AT CDNLive Munich, Robert Bosch presented on Hybrid Emulation in “IP and Driver Development in SOC alike Hybrid Environment” and at DAC 2017 in Austin we saw Uhnder present on “Cloud-Based SoC Emulation for Agile Software/Hardware Co-Development and Co-Verification” and Sirius XM Radio “Increasing 1st Pass Silicon Success with Full System Emulation and FPGA-based Prototyping.”

Continuing the worldwide tour of use models, CDNLive Japan featured Fujitsu’s Palladium Z1 usage as previously announced for Post-K Supercomputer Development and Renesas showing how they use Cadence Perspec for MCU verification on emulation. In Taiwan we saw Realtek combining High-Level Synthesis with Emulation and Mediatek “Enable Complex CPU System’s Coverage Closure by SW-Driven Stimulus with Structural Coverage Beyond Accelerated Emulator,” followed by CDNLive China where NHIDC illustrated their performance analysis results on Palladium Z1, while Huawei talked twice about Transaction Based Acceleration and how they “Use Cadence AVIP to Help Accelerate the System-Level Verification.” Phytium presented on their “PCIe System Level Test Method Based on Hardware Simulation Acceleration Platform.”

CDNLive Boston showed examples from ADI on how they do software development on Palladium for a Tensilica based design, a “Transactor Based Simulation Acceleration Cost Analysis and Performance Breakdown on Palladium Platform” by MicroSemi as well as Netronome’s sequel to their CDNLIve Silicon Valley presentation, this time focusing on “Accelerating Production Software Development Using Emulation.”

The most recent CDNLive was in India with six hardware related presentations. NXP presented twice on Hybrid Emulation to accelerate their OS boot-up down to just 2 minutes and on enabling software coverage using Palladium with a reusable and portable method between pre- and post-silicon. ARM detailed their Palladium Z1 usage with “Assertion-Based Verification of Arm 8.2 Cores on Palladium for System Level Stress Tests,” leading them to additional use models such as coverage driven verification. Broadcom showed “Combining UVM-Based Acceleration with In-Circuit Emulation for Thorough Validation Environment,” combining the best of two use modes into a single model – ICE and UVM-Acceleration. ADI described how they accelerated their embedded software development with Tensilica cores running in Palladium and Texas Instruments showed how they accelerated their Safety Software’s time-to-market of a Robust Functional Safe device with Palladium. In fact, they developed and unit tested their software in pre-silicon saving around a year of time, post silicon.

CDNLive Korea saw Samsung presenting on “What If You Can Speed Up Your Simulation Up to 50X?” outlining approaches to UVM Acceleration.

The year will be closing on November 7^th with CDNLive Israel, which will see two more related presentations – CEVA on “Advanced Multi-Platform Verification” outlining how they combine the core verification engines and Western Digital on “Product Performance Analysis Using Palladium Platform.”

That’s more than 30 customer experiences presented on in a year. And as you can see, there are well above 15 different use models here. Emulation truly has graduated and has become a versatile compute resource for verification, across application domains, hardware and software, IP to sub-system to SoC and system verification.