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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Apr. 3
By Jesse Allen - 03 Apr, 2024 - Comments: 0

Siemens' Keith Felton finds that high bandwidth memory integration poses significant challenges for package designers stemming from its unique architecture and stringent performance requirements. Synopsys' Gervais Fong finds out what's new in the USB4 v2 specification, some of its unique challenges involved in doubling the performance capabilities of the USB wired connection, and an intrigui... » read more

Research Bits: Apr. 2
By Jesse Allen - 02 Apr, 2024 - Comments: 0

Stretchy, sensitive circuits Researchers from Stanford University developed skin-like, stretchable integrated circuits capable of driving a micro-LED screen with a refresh rate of 60 Hz and detecting a braille array that is more sensitive than human fingertips. The stretchable transistors are made from semiconducting carbon nanotubes sandwiched between soft elastic electronic materials. The... » read more

Blog Review: Mar. 27
By Jesse Allen - 27 Mar, 2024 - Comments: 0

Cadence's Steve Brown suggests that multi-die technologies will be a key part of the path toward a faster, more efficient chip ecosystem that can support the compressed development cycles now emerging in the automotive industry. Synopsys' John Swanson, Madhumita Sanyal, and Priyank Shukla point to the role of simulation in ensuring seamless operation in the Ethernet ecosystem though rigorous... » read more

Research Bits: March 26
By Jesse Allen - 26 Mar, 2024 - Comments: 0

Skyrmion switches Researchers from the Agency for Science, Technology and Research (A*STAR) and National University of Singapore harnessed skyrmions to build a switch that has the potential to process data faster while using significantly less energy. Skyrmions are magnetic whirls that form in very thin metal layers and can be efficiently moved between magnetic regions. Using a magnetic tun... » read more

Blog Review: March 20
By Jesse Allen - 20 Mar, 2024 - Comments: 0

Synopsys' Kiran Vittal delves into AI chips, including the expansion of chip design beyond traditional semiconductor companies, adoption of RISC-V, and the use of formal equivalence checking to verify complex AI datapaths. Siemens' Patrick McGoff points to a survey that suggests projects deploying design for manufacturing within a PCB design flow are more likely to be completed on-time, on-q... » read more

Research Bits: Mar. 19
By Jesse Allen - 19 Mar, 2024 - Comments: 0

Superconducting loops Researchers from University of California San Diego and University of California Riverside propose using superconducting loops to store and transmit information in a method similar to the human brain. “Our brains have this remarkable gift of associative memory, which we don't really understand,” said Robert C. Dynes, professor of physics at UC San Diego and preside... » read more

Blog Review: Mar. 13
By Jesse Allen - 13 Mar, 2024 - Comments: 0

Cadence's Geeta Arora explains the Address Translation Service in PCIe 6.0, which allows an I/O device to perform its own virtual to physical address translations without relying on the host's CPU to reduce latency and improve overall system performance. Synopsys' John Swanson, Jon Ames, Priyank Shukla, and Varun Agrawal highlight the upcoming 1.6T iteration of the Ethernet standard and the ... » read more

Research Bits: Mar. 11
By Jesse Allen - 11 Mar, 2024 - Comments: 0

Ferroelectric nanosheets Engineers from the University of Sydney, RMIT University, University of New South Wales, and University of Technology Sydney created a liquid metal alloy of tin, zirconium, and hafnium. The alloy has a thin oxide layer crust that enables it to be used to harvest ultra-thin tin oxide nanosheets doped with hafnium zirconium oxide, which could then be 2D printed on a subs... » read more

Blog Review: Mar. 6
By Jesse Allen - 06 Mar, 2024 - Comments: 0

Synopsys' Gandharv Bhatara notes that successfully deploying high-NA EUV will rely on computational lithography to provide accurate modeling of aberrations, compact 3D mask modeling, and expand inverse lithography to full-chip processing. Cadence's John Park argues for using a systematic and automated system for co-design and co-analysis of multi-die packages to reduce the margin for human e... » read more

Startup Funding: February 2024
By Jesse Allen - 06 Mar, 2024 - Comments: 0

A startup developing AI chips dedicated to low-power AI inferencing captured one of the largest rounds of February. The startup, Recogni, already offers a low-power vision inferencing chip. Several other sizeable rounds were focused on the automotive space, with robotaxis, autonomous delivery, and the sensors that enable them. Another active area, power electronics drew funding for several c... » read more

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