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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Power/Performance Bits: June 27
By Jesse Allen - 27 Jun, 2017 - Comments: 0

Superconducting nanowire memory cell Researchers at the University of Illinois at Urbana-Champaign and the State University of New York at Stony Brook developed a new nanoscale memory cell that provides stable memory at a smaller size than other proposed memory devices, and holds promise for successful integration with superconducting processors. The device comprises two superconducting nan... » read more

The Week In Review: Design
By Jesse Allen - 23 Jun, 2017 - Comments: 0

M&A Silvaco will acquire SoC Solutions, adding more IP experience to the company's portfolio. SoC Solutions, based in Atlanta, GA, focuses on pre-configured IP subsystems and IP targeting low power IoT and machine-to-machine communication. Terms of the deal were not disclosed, but the acquisition is expected to close soon. Imagination is putting the rest of the company up for sale after... » read more

Blog Review: June 21
By Jesse Allen - 21 Jun, 2017 - Comments: 0

Mentor's John McMillan looks into the unique form-factors and components influencing IoT PCB designs. Cadence's Paul McLellan notes some big topics at the Samsung Foundry Forum: FD-SOI, embedded MRAM, and which gate-all-around FET architecture may be the winner. Synopsys' Eric Huang has a lighthearted look at why to buy IP versus building it. Rambus' Aharon Etengoff points to another U... » read more

Power/Performance Bits: June 20
By Jesse Allen - 20 Jun, 2017 - Comments: 0

Batteries from scrap metal Scientists at the Chinese Academy of Sciences and Jilin University found a method to transform rusty stainless steel mesh into electrodes with outstanding electrochemical properties that make them ideal for potassium-ion batteries. The rust is converted directly into a compact layer with a grid structure that can store potassium ions. A coating of reduced graphite... » read more

The Week In Review: Design
By Jesse Allen - 16 Jun, 2017 - Comments: 0

M&A Verific acquired Invionics' entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific. Portable Stimulus An Early Adopter release of the Portable Stimulus specification has been made publicly availabl... » read more

Blog Review: June 14
By Jesse Allen - 14 Jun, 2017 - Comments: 0

In a video, Cadence's Tom Hackett looks at the evolving von Neumann computer architecture and the development of CCIX driven by recent cloud computing challenges. Mentor's Puneet Sinha notes it's been 17 years since the Toyota Prius went on sale worldwide, and looks ahead to the next 17 years of electric vehicles. Synopsys' Sri Deepti Pisipati gives an overview of the different topologies... » read more

Power/Performance Bits: June 13
By Jesse Allen - 13 Jun, 2017 - Comments: 0

Theoretical all-carbon circuits Engineers at the University of Texas at Dallas, the University of Illinois at Urbana-Champaign, the University of Central Florida, and Northwestern University designed a novel computing system made solely from carbon. "The concept brings together an assortment of existing nanoscale technologies and combines them in a new way," said Dr. Joseph S. Friedman, ass... » read more

The Week In Review: Design
By Jesse Allen - 09 Jun, 2017 - Comments: 1

Tools Mentor added new tools to its high-level synthesis portfolio. The DesignChecks tool helps find bugs during coding with a static mode that performs very fast linting-like checks of the code and a formal mode that uses a formal engine for a more exhaustive proof of issues. The synthesis-aware Coverage tool measures code coverage for C++ signoff and fast closure of synthesized RTL. It sup... » read more

Blog Review: June 7
By Jesse Allen - 07 Jun, 2017 - Comments: 0

Cadence's Paul McLellan listens in on Jeff Bier's Embedded Vision Summit keynote, where he argues the cost and power consumption of vision computing will decrease by about 1000X in the next three years. Synopsys' Sean Safarpour points to three reasons formal has grown in the last ten years to become a standard part of the verification toolbox. Mentor's Matthew Balance checks out the abili... » read more

Power/Performance Bits: June 6
By Jesse Allen - 06 Jun, 2017 - Comments: 0

Magnetoelectric RAM A team of researchers from the Institute of Electronics, Microelectronics and Nanotechnology in Lille, France and the Russian Academy of Sciences in Moscow developed a magnetoelectric random access memory (MELRAM) cell that has the potential to increase power efficiency, and thereby decrease heat waste, by orders of magnitude for read operations at room temperature. Th... » read more

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