The Week In Review: Design

Verific acquires Invionics platform; Portable Stimulus early adopters release; DAC; multimode CDC; safety-critical MIPS core.

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M&A
Verific acquired Invionics’ entire INVIO technology portfolio, adding a high-level scripting interface with 100 high-level APIs to its Parser Platform of approximately 2,000 low-level SystemVerilog and VHDL APIs. An R&D group from the company will also join Verific.

Portable Stimulus
An Early Adopter release of the Portable Stimulus specification has been made publicly available. The specification defines a standard mechanism for the specification of verification intent and behaviors that would be reusable across target platforms and allow for the automation of test generation. The specification provides a comprehensive explanation of the new Portable Stimulus Domain Specific language and equivalent C++ Class Library. The working group will be accepting feedback and comments until Friday, September 15, 2017 before finalizing the specification for release in early 2018.

Mentor expanded the technology across its full Enterprise Verification Platform and has provided a list of Portable Stimulus-focused events at DAC, including Verification Academy sessions.

Breker will showcase its implementation of the standard at DAC along with two new prepackaged applications designed to test multicore ARMv8 systems as well as transition sequences in complex power management state machines.

For more on Portable Stimulus at DAC, Cadence will be hosting several discussions and demonstrations at the Cadence theater with a focus on Perspec support for the standard.

Tools
Real Intent revealed a new multimode clock domain crossing (CDC) sign-off solution for RTL designs. According to the company, Verix CDC provides one-step analysis and debug of all operating modes in an IC and employs a new architecture for multimode analysis with static intent verification technology. Additional products will be introduced in the future that employ the new verification architecture.

At DAC, Teklatech is revealing new timing optimization features for its dynamic voltage drop tool, FloorDirector.

Mentor’s Oasys-RTL, Nitro-SoC and FormalPro digital implementation and verification tools achieved ISO 26262 qualification.

IP
Imagination unveiled a highly-scalable 64-bit MIPS multiprocessing CPU IP targeted at safety-critical systems. The company says the I6500-F core is capable of powering AI techniques such as CNNs and DNNs in autonomous vehicles, and was validated to meet functional safety compliance for ISO 26262 and IEC 61508 standards. Mobileye’s upcoming EyeQ5 SoC for autonomous vehicles is based on the I6500-F CPU.

Avery Design Systems launched DDR5 VIP that supports DDR5 SoC, memory controller, and DFI-PHY designs. The company also uncorked VIP for the MIPI I3CSM sensor interface specification, which supports master and slave design verification, I3C specification Version 1.0 and I3C Host Controller Interface (HCI) draft Version 0.5.

Arasan debuted its SD Card UHS-II IP core. Specially optimized for area and power, the IP is fully compliant to SD Associations v5.1 and physical layer v5.0. UHS-II PHY operates in either half or full duplex, achieving a one way peak bandwidth of 3.12Gbps or two way bandwidth of 1.56Gbps, over a two-wire SERDES interface.

Silab Tech released a SerDes IP core to provide a symmetrical 10Gbps interconnect solution for Next Generation Passive Optical Networks (PON). XGS-PON PHY was tested on silicon to comply with the ITU-T G.9807.1 “10-Gigabit-capable symmetric passive optical network” standard.

Numbers
Achronix is expecting a rosy future, predicting revenue growth of over 700% year over year with revenue exceeding $100M in 2017. The FPGA and eFPGA accelerator company reached profitability in Q1 2017.

Deals
Toshiba adopted Synopsys’ SVA based formal verification tool for the development of leading-edge automotive devices and storage products, citing performance, capacity and ease-of-use.

PhoeniX Software’s platform to synthesize photonics circuits based on correct-by-construction algorithms, OptoDesigner, is now integrated with Mentor’s Calibre to allow Calibre verification to run directly in OptoDesigner.