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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Research Bits: Dec. 13
By Jesse Allen - 13 Dec, 2022 - Comments: 0

Electronic-photonic interface for data centers Engineers at Caltech and the University of Southampton integrated an electronic and photonic chip for high-speed communication in data centers. "There are more than 2,700 data centers in the U.S. and more than 8,000 worldwide, with towers of servers stacked on top of each other to manage the load of thousands of terabytes of data going in and o... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Startup Funding: November 2022
By Jesse Allen - 07 Dec, 2022 - Comments: 0

November was a month for mega-rounds, with ten companies receiving investments of at least $100 million. One of those is a startup providing connectivity solutions for data centers and enabling use of the memory pooling functionality in the latest update to the CXL standard. Two quantum computer startups were part of the $100M+ club this month — one using very cold atoms to take on not only q... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Research Bits: Dec. 5
By Jesse Allen - 05 Dec, 2022 - Comments: 0

Protonic programmable resistors for AI Researchers from the Massachusetts Institute of Technology (MIT) developed an analog deep learning processor based on protonic programmable resistors arranged in an array. In the processor, increasing and decreasing the electrical conductance of protonic resistors enables analog machine learning. The conductance is controlled by the movement of protons... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2022 - Comments: 0

Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Blog Review: Nov. 23
By Jesse Allen - 23 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at multiple data points to get a sense of effort spent in FPGA verification and increasing demand for FPGA verification engineers. Synopsys' Rimpy Chugh, Himanshu Kathuria, and Rohit Kumar Ohlayan argue that the quality of the design and testbench code is critical to a project’s success and that linting offers a comprehensive checking process for teams to s... » read more

Research Bits: Nov. 21
By Jesse Allen - 21 Nov, 2022 - Comments: 0

Graphene heater for phase-change switches Researchers from the University of Washington, Stanford University, Charles Stark Draper Laboratory, University of Maryland, and Massachusetts Institute of Technology designed an energy-efficient, silicon-based non-volatile switch that manipulates light through the use of a phase-change material and graphene heater. Aiming to reduce the power consum... » read more

Blog Review: Nov. 16
By Jesse Allen - 16 Nov, 2022 - Comments: 0

Siemens EDA's Jake Wiltgen explains the difference between transient and permanent faults when designing to the ISO 26262 standard, including where they come from and key ways to protect against them. Synopsys' Vikas Gautam points to how the economics of designing large SoCs is driving chiplet-based designs and the need for die-to-die standards such as UCIe, along with the key protocol verif... » read more

Research Bits: Nov. 15
By Jesse Allen - 15 Nov, 2022 - Comments: 0

Low temperature 3D bonding Scientists from Osaka University developed a new method for the direct three-dimensional bonding of copper electrodes using silver layers. The method works at low temperatures and does not require external pressure. "Our process can be performed under gentle conditions, at relatively low temperatures and without added pressure, but the bonds were able to withstand... » read more

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