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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Nov. 9
By Jesse Allen - 09 Nov, 2022 - Comments: 0

Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

Research Bits: Nov. 7
By Jesse Allen - 07 Nov, 2022 - Comments: 0

ADC side-channel attacks Researchers at MIT propose two ways to protect analog-to-digital converters (ADCs) from power and electromagnetic side-channel attacks. The researchers first investigated the side-channel attacks that could be used against ADCs. Power attacks usually involve an attacker soldering a resistor onto the device’s circuit board to measure its power usage. An electromagn... » read more

Startup Funding: October 2022
By Jesse Allen - 02 Nov, 2022 - Comments: 1

Investors poured $3.5 billion into 113 startup companies in October 2022, especially new battery technology, AI hardware, and faster memory access. Battery technology dominated the fundraising in October thanks to the U.S. Department of Energy and four funding rounds that exceeded $200M. The DOE awarded sizeable grants to help 20 companies, including six startups, build out battery material ... » read more

Blog Review: Nov. 2
By Jesse Allen - 02 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster examines how successful FPGA projects are in terms of verification effectiveness, finding that only 16% of all FPGA projects were able to achieve no non-trivial bug escapes into production, worse than IC/ASIC in terms of first silicon success. Synopsys' Jamie Boote and The Chertoff Group's David London break down best practice guidance and directives U.S. governmen... » read more

Blog Review: Oct. 26
By Jesse Allen - 26 Oct, 2022 - Comments: 0

Synopsys' Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP. Siemens EDA's Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on t... » read more

Research Bits: Oct. 25
By Jesse Allen - 25 Oct, 2022 - Comments: 0

Polarization for photonic processor Researchers from the University of Oxford and University of Exeter developed a photonic processor that uses multiple polarization channels, increasing information density. "We all know that the advantage of photonics over electronics is that light is faster and more functional over large bandwidths. So, our aim was to fully harness such advantages of phot... » read more

Blog Review: Oct. 19
By Jesse Allen - 19 Oct, 2022 - Comments: 0

Siemens EDA's Harry Foster examines trends related to various aspects of FPGA design and the growing design complexity associated with increasing number of embedded processor cores, asynchronous clock domains, and more safety features. Synopsys' Twan Korthorst and Kenneth Larsen take a broad look at silicon photonics, including the benefits of electronic integration, accelerating the develop... » read more

Research Bits: Oct. 18
By Jesse Allen - 18 Oct, 2022 - Comments: 0

Modular AI chip Engineers at the Massachusetts Institute of Technology (MIT), Harvard University, Stanford University, Lawrence Berkeley National Laboratory, Korea Institute of Science and Technology, and Tsinghua University created a modular approach to building stackable, reconfigurable AI chips. The design comprises alternating layers of sensing and processing elements, along with LEDs t... » read more

Week In Review: Design, Low Power
By Jesse Allen - 14 Oct, 2022 - Comments: 0

Cadence unveiled a new environment to automate and accelerate the complete design closure cycle from signoff optimization through routing, static timing analysis (STA), and extraction. The Certus Closure Solution allows concurrent, full-chip optimization through a massively parallel and distributed architecture and engine shared with Cadence’s Innovus Implementation System and the Tempus Timi... » read more

Blog Review: Oct. 12
By Jesse Allen - 12 Oct, 2022 - Comments: 0

Synopsys' Richard Solomon, Madhumita Sanyal, and Gary Ruggles take a look at the possibilities that CXL 3.0 can bring to a variety of data-driven applications that demand increasingly higher levels of memory capacity, with higher bandwidth, more security, and lower latency. Siemens EDA's Rich Edelman provides some tips for debugging UVM testbenches, such as how to determine what line changed... » read more

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