Blog Review: Nov. 23

FPGA verification effort; linting testbench code; memory protection; software test libraries.


Siemens EDA’s Harry Foster looks at multiple data points to get a sense of effort spent in FPGA verification and increasing demand for FPGA verification engineers.

Synopsys’ Rimpy Chugh, Himanshu Kathuria, and Rohit Kumar Ohlayan argue that the quality of the design and testbench code is critical to a project’s success and that linting offers a comprehensive checking process for teams to spot fundamental issues early on.

Cadence’s Paul McLellan checks out the CHERI project to improve memory protection and Arm’s Morello implementation, along with what had to change from the typical Arm processor architecture.

Arm’s James Scobie highlights the role of software test libraries in assuring functional safety by testing the hardware for the presence of permanent faults within the processor functional logic, such as stuck at one and stuck at zero faults.

Ansys’ Kim Woodham and Laura Carter argue that ensuring the safety of autonomous vehicles requires extensive testing and validation via simulation of the sensors and perception software that enable behavior prediction and object recognition.

In a video, SEMI’s Heidi Hoffman shares a talk from Al Gore on how collaboration in the semiconductor value chain can help sustainability, along with a panel discussion with members of the recently-formed Semiconductor Climate Consortium.

Intel’s Brian Aspnes finds that modular server architectures could be a solution to meet conflicting requirements and introduces an effort at the Open Compute Project to define Host Processor Modules that can be used with other elements to configure a full server.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials and Systems & Design newsletters:

Technology Editor Brian Bailey contends that even though standards are rarely created for the benefit of the industry, that can be a useful by-product.

Amkor’s Prasad Dhond explains why copper is superior to gold in automotive applications.

Calibra’s Jan Willis looks at the impact of EUV on mask spend, increasing use of pellicles, and whether circular masks are on the horizon.

Lam Research’s Sumant Sarkar investigates how etch depth and other etch process parameters affect parasitic capacitance.

Promex’s Dick Otte shows how to incorporate parts that have unique chemistries, optical characteristics, or specialized requirements into biotech devices.

The Electronic System Design Alliance’s Bob Smith examines the impact of hardware-assisted verification and the growth of semiconductor R&D spending on EDA fortunes.

Siemens EDA’s Bill Acito observes that a clear-cut delineation between silicon die design and IC packaging design no longer exists.

Synopsys’ Bradley Geden predicts that multi-die technology will be the next major advance in semiconductor design productivity.

Cadence’s Neil Zaman looks at the role of digital twins in reducing data center power consumption.

Renesas’ Sailesh Chittipeddi finds that transforming data at the source of collection minimizes latency and enables optimized processing for time-critical applications.

Codasip’s Lauranne Choquin explains why more students should focus on electronics.

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