Alternative Text

Jesse Allen

  (all posts)
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Sept. 8
By Jesse Allen - 08 Sep, 2021 - Comments: 0

Synopsys' Scott Durrant considers the IP used in HPC SoCs and the efforts to simultaneously minimize data movement and maximize the speed at which data is transferred from one location to another, whether that data transfer is across long distances or from one chip to another within a server. Cadence's Paul McLellan looks into a new version of the Rowhammer DRAM vulnerability that can allow ... » read more

Power/Performance Bits: Sept. 8
By Jesse Allen - 08 Sep, 2021 - Comments: 0

Backscatter radios for 5G Researchers at the Georgia Institute of Technology, Nokia Bell Labs, and Heriot-Watt University propose using backscatter radios to support high-throughput communication and 5G-speed Gb/sec data transfer using only a single transistor. “Our breakthrough is being able to communicate over 5G/millimeter-wave (mmWave) frequencies without actually having a full mmWave... » read more

Week In Review: Design, Low Power
By Jesse Allen - 03 Sep, 2021 - Comments: 0

Synaptics will acquire DSP Group, a provider of voice and wireless chipset solutions for converged communications, at $22.00 per share in an all-cash transaction. The deal is worth $538 million. "We continue to invest in technologies that tilt our product mix toward IoT applications," said Michael Hurlston, President and CEO of Synaptics. "DSP Group's expertise in SmartVoice and ULE wireless so... » read more

Blog Review: Sept. 1
By Jesse Allen - 01 Sep, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava continue their exploration of MRAM simulation by explaining stochasticity experiments and a characterization framework that focuses on the MRAM behavior statistical analysis. Siemens EDA's Neil Johnson shows how performance profiling can be used to identify testbench code that could slow down simulation and when to start using i... » read more

Startup Funding: August 2021
By Jesse Allen - 01 Sep, 2021 - Comments: 0

More than $3.5 billion in funding was funneled into 35 startups last month, much of that scattered across the globe. Several Chinese companies received significant funding as the country bulks up domestic production of wafers and GPUs. In addition, with attention increasing on the need for electric vehicles and renewable energy, big investments went into battery manufacturing startups. One comp... » read more

Power/Performance Bits: Aug. 31
By Jesse Allen - 31 Aug, 2021 - Comments: 0

Securing memory Researchers at Columbia University suggest several ways to make computing more secure without imposing a system performance penalty. The efforts focus on memory security, specifically pointers. "Memory safety has been a problem for nearly 40 years and numerous solutions have been proposed. We believe that memory safety continues to be a problem because it does not distribute... » read more

Week In Review: Design, Low Power
By Jesse Allen - 27 Aug, 2021 - Comments: 0

The UK's Competition and Markets Authority is raising new challenges for Nvidia's proposed acquisition of Arm, suggesting in a new report that an in-depth Phase 2 investigation into the deal is warranted on competition grounds. Andrea Coscelli, chief executive of the CMA, said, “We’re concerned that Nvidia controlling Arm could create real problems for Nvidia's rivals by limiting their acce... » read more

Blog Review: Aug. 25
By Jesse Allen - 25 Aug, 2021 - Comments: 0

Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Power/Performance Bits: Aug. 24
By Jesse Allen - 24 Aug, 2021 - Comments: 0

Low power AI Engineers at the Swiss Center for Electronics and Microtechnology (CSEM) designed an SoC for edge AI applications that can run on solar power or a small battery. The SoC consists of an ASIC chip with RISC-V processor developed at CSEM along with two tightly coupled machine-learning accelerators: one for face detection, for example, and one for classification. The first is a bin... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy