Blog Review: Sept. 1

MRAM behavior, performance profiling, co-design of multi-die chips.


Arm’s Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava continue their exploration of MRAM simulation by explaining stochasticity experiments and a characterization framework that focuses on the MRAM behavior statistical analysis.

Siemens EDA’s Neil Johnson shows how performance profiling can be used to identify testbench code that could slow down simulation and when to start using it.

Cadence’s Paul McLellan listens in on a presentation from the BlackHat security conference that demonstrates how security flaws in common devices made it possible to hack a neighbor’s capsule hotel room.

Synopsys’ Manuel Mota and Kenneth Larsen consider what’s driving the move to multi-die chip designs and why it’s important to co-design them with an upfront understanding of thermal footprint, signal and power integrity, mechanical issues, routing considerations, and other key parameters.

Ansys’ Theresa Duncan and Kelly Morgan show a semi-automated model generation workflow for exporting high-fidelity, fully meshed PCB models to tools that can perform drop tests and other analyses.

Coventor’s Pradeep Nanja points to how high accuracy capacitance segmentation can be used to identify net segments that have an unacceptable cross-capacitance and proactively change process steps or device design features to improve those results.

SEMI’s Serena Brischetto chats with Intel’s Kaladhar Radhakrishnan about global market trends driving demand for heterogenous system integration and some of the key technology challenges still ahead.

Plus, check out the blogs featured in the latest S&D newsletter:

Technology Editor Brian Bailey contends that learning how to learn is a skill that often falls through the cracks, and yet it is the most valuable skill you can have.

Cadence’s Frank Schirrmeister predicts decisions about 6G will need to be made sooner than one might think.

Synopsys’ Taruna Reddy explains the importance of keeping ahead of growing debug complexity with features like partial design loading and intelligent visualization.

Siemens EDA’s Rob van Blommestein endorses automated formal code inspection for early detection of implementation issues.

Codasip’s Roddy Urquhart compares adding toppings to your pizza versus hiring a private chef.

Siemens EDA’s Srinivas Velivala shows how to bring signoff-quality DRC into custom and analog/mixed-signal design flows.

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