中文 English

Blog Review: Sept. 8

IP in HPC; half-double Rowhammer; faster testbenches; MBTF vs. reliability analysis.

popularity

Synopsys’ Scott Durrant considers the IP used in HPC SoCs and the efforts to simultaneously minimize data movement and maximize the speed at which data is transferred from one location to another, whether that data transfer is across long distances or from one chip to another within a server.

Cadence’s Paul McLellan looks into a new version of the Rowhammer DRAM vulnerability that can allow an attack to flip bits two rows away from the one being attacked, rather than the immediately adjacent row as in the original exploit.

Siemens EDA’s Neil Johnson points to reasons to build a simulation performance profile to help make testbenches faster, plus a tutorial for getting started.

Ansys’ Tyler Ferris finds the potential consequences of using only handbook-based mean time between failure analysis and the advantages of incorporating simulation for product reliability analysis, such as detailed model inputs and load applications.

Arm’s Stephan Waldert explains how the company is trying to use machine learning and data science techniques to reduce the energy consumption and improve efficiency of its IP development workflows.

Memory analyst Jim Handy considers whether a new technology from Intel can help bring down the cost of high-bandwidth memory and make it affordable enough to use in more products.

Nvidia’s Kevin Deierling argues that as AI applications and the software-defined revolution rise, so does the value of new chip architectures.

And don’t miss the blogs featured in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Infineon’s Thomas Poeppelmann and Martin Schlaeffer warn not to wait for quantum-resistant cryptography standards to be developed.

Xilinx’s Awanish Verma looks at the implementation of the fronthaul and L1 Hi-PHY for 5G base stations.

Siemens EDA’s Lee Harrison sees the requirements around secure test and monitoring becoming mainstream.

Flex Logix’s Sam Fuller contends that as AI models continue to expand in complexity and size, tiny inefficiencies get multiplied into large ones.

Synopsys’ Anand Thiruvengadam examines why it’s getting so difficult to develop discrete memory chips and what to do about it.

Rambus’ Neeraj Paliwal explains why protecting 5G-connected AI devices requires a fundamental change in the way we think about security.

Siemens EDA’s Rob van Blommestein advises managing security throughout the IP lifecycle.

Onto’s Woo Young Han contends that new fabs for 28nm node production point to a boom in AR/VR devices.

Siemens EDA’s Geir Eide sees the bus-based scan data distribution taking the world by storm.



Leave a Reply


(Note: This name will be displayed publicly)