The Era Of Packetized Scan Test Has Arrived

Bus-based scan data distribution takes the world by storm.


For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression became the norm to address test data time and volume. Over the last decade, hierarchical DFT enabled DFT engineers to apply a divide and conquer on large design, improving both implementation effort and test cost. Today, the industry is going through a similar transformation, the adoption of packetized scan test delivery. Driving this transition is the continued design scaling, which makes effective implementation of hierarchical DFT extraordinarily time consuming, along with newer implementation styles, such as tiled design with abutment, and 2.5D/3D packaging.

The Streaming Scan Network, introduced less than one year ago by Siemens Digital Industries Software, is the first commercial full-flow implementation of packetized scan test. In the year since its introduction, the industry has adopted this technology faster than any other comparable transformative DFT technology, including embedded deterministic test (EDT).

Streaming Scan Network (SSN) consists of a bus that delivers scan test data across the SoC, and a host node inside each core that picks up and returns data from the bus. This implementation decouples the DFT requirements of individual cores from the chip-level test delivery resources. Figure 1 illustrates the basic architecture of SSN.

At the International Test Conference 2020, Intel reported the results of their evaluation of SSN. Comparing the SSN method to their traditional pin-mux approach, they report a reduction in test data volume of 43% and a reduction of test cycles of 43%. Implementation and test retargeting tasks were between 10x-20x faster. At the upcoming International Test Conference 2021 (ITC), a number of other SSN users will present their experiences.

Overview of packetized scan test
Unlike the traditional approach to delivering scan test data to cores in which each core requires a dedicated connection to chip-level pins, SSN delivers scan data as packets across a shared bus. This creates a very efficient and tunable system. Designers do not need to allocate a fixed number of scan channels for each core or worry about the potential for routing congestion.

SSN delivers scan test data across a uniform network that is connected to all cores or blocks in a design. The data that is shifted in and out of the chip does not look like conventional scan test data but is organized in packets and translated into more conventional-looking scan data at each core.

With SSN, test controllers are local; core-level host nodes generate the DFT signals locally, ensure that the right data is picked up from the bus and sent to scan inputs of the core and that the output data is placed back onto the bus. Each node knows what to do and when to do it based on a simple configuration step leveraging IJTAG (IEEE 1687) infrastructure.

Benefits vs. cost of adoption
Some new technologies are difficult, expensive, or risky to implement. The variables that go into the cost/benefit analysis are many and specific to each chip maker. The pressures of chip design today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferation of identical cores and tiled designs—all go into the calculation. The challenges of tomorrow—re-use of high-speed I/Os for scan test, testing 3D ICs, and increased bandwidth for non-scan test—should also be considered.

What SSN has going for it as a solution to these challenges is the high level of automation, compatibility with existing DFT and design flows, a common architecture for all design types, and solid support from the supplier. Many of the leading semiconductor companies have already done the math and decided to adopt the Tessent SSN packetized test solution.

Specific benefits of SSN include cutting DFT development time in half, easing routing and timing closure, and reducing test time and test data by up to 4X.

The SSN approach is based on the principle of decoupling core-level test requirements from chip-level test resources by using a high-speed synchronous bus to deliver packetized scan test data to the cores. It was developed in collaboration with leading semiconductor companies to bring scan test data delivery into the fast lane.

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