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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Power/Performance Bits: July 27
By Jesse Allen - 27 Jul, 2021 - Comments: 0

Amplifying light for lidar Engineers at University of Texas at Austin and University of Virginia developed a light detector that can amplify weak light signals and reduce noise to improve the accuracy of lidar. "Autonomous vehicles send out laser signals that bounce off objects to tell you how far away you are. Not much light comes back, so if your detector is putting out more noise than th... » read more

Week In Review: Design, Low Power
By Jesse Allen - 23 Jul, 2021 - Comments: 0

Tools Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL-to-signoff implementation flow. The tool aims to use reinforcement learning to find flow solutions that otherwise might not be explored and applies models to future designs. The company says it can improve productivity up to 10X and PPA up to 20% with optimization of the flow f... » read more

Blog Review: July 21
By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

Power/Performance Bits: July 20
By Jesse Allen - 20 Jul, 2021 - Comments: 0

Shrinking RFID chips Researchers at North Carolina State University built a new, tiny RFID chip. They expect the chip to help drive down costs for RFID tags, making it possible to embed them in more things for supply chain security. "As far as we can tell, it's the world's smallest Gen2-compatible RFID chip," said Paul Franzon, Professor of Electrical and Computer Engineering at NC State. I... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Jul, 2021 - Comments: 0

Tools Andes Technology certified Imperas reference models for the complete range of Andes IP cores with the new RISC-V P SIMD/DSP extension. The reference models can be used to evaluate multicore design configuration options for SoC architecture exploration and support early software development before silicon prototypes are available. Cadence's digital full flow was optimized and certified... » read more

Blog Review: July 14
By Jesse Allen - 14 Jul, 2021 - Comments: 0

Siemens EDA's Wei-Lii Tan considers the tradeoffs when running library characterization in the cloud and how to think about running CPUs in parallel, the cost of throughput, and runtime reductions. A Synopsys writer checks out the reduced blanking feature in HDMI 2.1, which can help reduce the transmission rate while keeping the resolution and refresh rate intact for higher resolution displa... » read more

Power/Performance Bits: July 13
By Jesse Allen - 13 Jul, 2021 - Comments: 0

Graphene PUFs Researchers at Pennsylvania State University propose using graphene to create physically unclonable functions (PUFs) that are energy efficient, scalable, and secure against AI attacks. The team first fabricated nearly 2,000 identical graphene transistors. Despite their structural similarity, the transistors' electrical conductivity varied due to the inherent randomness arising... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Jul, 2021 - Comments: 0

Tools Aldec extended its TySOM family of embedded prototyping boards with the introduction of TySOM-M-MPFS250, the first in a planned series to feature a Microchip PolarFire SoC FPGA MPFS250T-FCG1152 and to have dual FMC connectivity. The board contains 16Gb FPGA DDR4 x32, 16Gb MSS DDR4 x36 with ECC, eMMC, SPI Flash memory, 64 Kb EEPROM and a microSD card socket. The PolarFire SoC is a five-st... » read more

Startup Funding: June 2021
By Jesse Allen - 07 Jul, 2021 - Comments: 0

June was the month of mega-rounds for autonomous driving companies, with three pulling in well over $100M. All three are based in China, but their products range from chips to full robotaxi services. Also in the automotive space, an EV battery manufacturer raised over $2B, a solid-state lidar developer drew $300M — and those are just the largest rounds. Plus, new HPC architectures, GAA metrol... » read more

Blog Review: July 7
By Jesse Allen - 07 Jul, 2021 - Comments: 0

Cadence's Sangeeta Soni provides a primer on the PIPE SerDes architecture and some of the changes that can introduce verification challenges for SerDes compliant PHY and MAC devices. Siemens EDA's Chris Spear demystifies the $cast() method in SystemVerilog, which checks values at runtime rather than compile time, and gives some examples of when it is useful. Synopsys' Chris Clark warns th... » read more

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