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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Blog Review: Dec. 16
By Jesse Allen - 16 Dec, 2020 - Comments: 0

Arm's Benoit Labbe investigates why battery monitoring is so important for a low-power microcontroller and shows how it was implemented in the M0N0 MCU while drawing a fraction of a nW in typical conditions. Siemens EDA's Harry Foster takes a look at how much of their time FPGA design engineers spend on verification, and the tasks that keep verification engineers the busiest. Synopsys' Sc... » read more

Power/Performance Bits: Dec. 15
By Jesse Allen - 15 Dec, 2020 - Comments: 0

Graphite films for cooling electronics Researchers at King Abdullah University of Science and Technology (KAUST) developed a way to make a carbon material well suited to dissipating heat in electronic devices. Graphite films are frequently used for heat management. "However, the method used to make these graphite films, using polymer as a source material, is complex and very energy intensiv... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Dec, 2020 - Comments: 0

RISC-V RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, S... » read more

Blog Review: Dec. 9
By Jesse Allen - 09 Dec, 2020 - Comments: 0

Arm's Benoit Labbe digs into designing a power converter for Arm Research's ultra-low power M0N0 microcontroller, with a focus on optimal efficiency and leakage constraints. Mentor's Harry Foster tries to get a sense of how much effort is spent in verification of FPGAs by looking at the amount of time spent and number of engineers on a project. Cadence's Paul McLellan listens in as Odile ... » read more

Power/Performance Bits: Dec. 7
By Jesse Allen - 07 Dec, 2020 - Comments: 0

Logic-in-memory with MoS2 Engineers at École Polytechnique Fédérale de Lausanne (EPFL) built a logic-in-memory device using molybdenum disulfide (MoS2) as the channel material. MoS2 is a three-atom-thick 2D material and excellent semiconductor. The new chip is based on floating-gate field-effect transistors (FGFETs) that can hold electric charges for long periods. MoS2 is particularly se... » read more

Week In Review: Design, Low Power
By Jesse Allen - 04 Dec, 2020 - Comments: 0

Xilinx acquired the assets of Falcon Computing Solutions, a provider of high-level synthesis (HLS) compiler optimization technology for hardware acceleration of software applications. The acquisition will be integrated into the Xilinx Vitis Unified Software Platform to automate hardware-aware optimizations of C++ applications with minimal hardware expertise. “Our compiler provides a high degr... » read more

Startup Funding: November 2020
By Jesse Allen - 02 Dec, 2020 - Comments: 0

Numerous chipmakers pulled in funding in November 2020, with investors putting money into interconnects, memories, AI hardware, and quantum computing. Launching from stealth was a startup aiming to combine AI and 5G. Autonomous delivery did well, too, with one company raising a massive $500M. This month, we take a look at 28 companies that raised a collective $1.1B. Semi & design Connec... » read more

Blog Review: Dec. 2
By Jesse Allen - 02 Dec, 2020 - Comments: 0

Mentor's Harry Foster investigates the effectiveness of today’s FPGA verification processes in terms of nontrivial bug escapes into production as part of the 2020 Wilson Research Group Functional Verification Study. Synopsys' Chris Clark points to how integral sensors are to the modern vehicle and key design considerations for making them more effective, safe, and reliable. Cadence's Pa... » read more

Power/Performance Bits: Dec. 1
By Jesse Allen - 01 Dec, 2020 - Comments: 0

Self-erasing chip Researchers from the University of Michigan developed self-erasing chips that could be used to prevent counterfeiting or detect tampering. The technology is based on a new material that temporarily stores energy, changing the color of the light it emits. It self-erases in a matter of days, or it can be erased on demand. "It's very hard to detect whether a device has been t... » read more

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