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Blog Review: Dec. 16

Battery monitoring and MCUs; FPGA verification; die-to-die connectivity; high bandwidth interconnect.

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Arm’s Benoit Labbe investigates why battery monitoring is so important for a low-power microcontroller and shows how it was implemented in the M0N0 MCU while drawing a fraction of a nW in typical conditions.

Siemens EDA’s Harry Foster takes a look at how much of their time FPGA design engineers spend on verification, and the tasks that keep verification engineers the busiest.

Synopsys’ Scott Durrant and Manmeet Walia explain why large HPC designs are moving toward die-to-die connectivity and multi-chip modules and the differences between homogeneous dies and heterogeneous dies.

Cadence’s Paul McLellan checks out High Bandwidth Interconnect, a new proposed general standard from ODSA OpenHBI Initiative for die-to-die communication that leverages work done on the existing JEDEC HBM standard.

Ansys’ Anthony Dawson and Joe Sheehan explain how mission simulation expands engineering simulation to the operational environment to ensure that interdependent systems work properly with each other before physical prototyping.

In a blog for SEMI, John West of VLSI Research finds that despite unprecedented supply chain disruptions, critical subsystems for semiconductor equipment are set to exceed $12.2 billion in sales this year, with vacuum valves, chillers, and optical fiber thermometry likely to grow above 35%.

Nvidia’s Cliff Edwards listens in on what the experts predict for AI adoption in 2021, from treating AI as a compiler, new opportunities for data scientists, and applications including robots and healthcare

NXP’s Lars Reger explores how 5G, Wi-Fi 6, UWB, and NFC wireless technologies are working in concert to speed access to railways and public transit as well as providing a better experience while on board.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Siemens EDA’s Russell Klein identifies significant contributors to performance and efficiency for custom developed hardware inferencing accelerators.

Synopsys’ Vadhiraj Sankaranarayanan explains how side-band, inline, on-die, and link error correcting schemes work and the applications to which they are best suited.

Fraunhofer’s Jens Michael Warmuth contends that rethinking of classic concepts is required for autonomous vehicles to be affordable.

Cadence’s Paul McLellan looks at how to make photonics chips compatible with existing OSAT assembly and test lines.

Arm’s Dylan Zika warns that a lack of a common understanding of performance is hampering AI growth.

Rambus’ Joseph Rodriguez goes under the hood of an HBM2E memory interface with enough bandwidth for AI and HPC applications.

Ansys’ Susan Coleman shows how a Spanish startup is taking on designing the ground transportation system of the future.

Xilinx’s Quenton Hall examines critical memory access considerations when implementing inference accelerators.

OneSpin’s Sergio Marchese explains why addressing security-relevant hardware weaknesses is crucial to designing vulnerability-free IPs and chips.

Synopsys’ Hari Sathianathan explores using symbolic simulation technology to validate power domain interfaces in custom memories.

Ansys’ Denis Soldo stresses the importance of keeping your simulation software up to date.

Synopsys’ Joe Mallett explains how to ensure that safety-critical designs can detect and recover from errors.



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