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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 27 Nov, 2020 - Comments: 0

AI Mythic debuted its Analog Matrix Processor for edge AI applications such as smart home, AR/VR, drones, video surveillance, smart city, and industrial. The M1108 AMP combines 108 tiles made up of an array of flash cells and ADCs, a 32-bit RISC-V nano-processor, a SIMD vector engine, SRAM, and a high-throughput Network-on-Chip router. It uses 40nm technology and the company says typical power... » read more

Blog Review: Nov. 25
By Jesse Allen - 25 Nov, 2020 - Comments: 0

Mentor's Harry Foster finds growing complexity in FPGA design by looking at the number of embedded microprocessors, asynchronous clock domains, and safety/security features in the 2020 Wilson Research Group Functional Verification Study. Cadence's Paul McLellan points to the interim SRC/SIA Decadal Plan for Semiconductors and five big shifts it identifies in information and communication tec... » read more

Power/Performance Bits: Nov. 23
By Jesse Allen - 23 Nov, 2020 - Comments: 0

Graphene energy Researchers from the University of Arkansas, University of Pennsylvania, and Universidad Carlos III de Madrid built a circuit capable of capturing graphene's thermal motion and converting it into an electrical current. "An energy-harvesting circuit based on graphene could be incorporated into a chip to provide clean, limitless, low-voltage power for small devices or sensors,... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Nov, 2020 - Comments: 0

Synopsys acquired Light Tec, a provider of optical scattering measurements and measurement equipment. The company also provides optical engineering consulting services plus training for use of Synopsys' lighting simulation software. "Light Tec's proven optical measurement capabilities provide our customers with robust new tools for high-accuracy optical product simulations and visualizations," ... » read more

Blog Review: Nov. 18
By Jesse Allen - 18 Nov, 2020 - Comments: 0

Arm's Roberto Lopez Mendez finds that holographic displays can now be achieved on mobile processors thanks to recent algorithmic and computational advances. Mentor's Colin Walls examines the reasons the consolidate a number of automotive sub-systems onto a smaller number of powerful ECU to reduce complexity and increase system reliability. Cadence's Paul McLellan takes a look at the devel... » read more

Power/Performance Bits: Nov. 17
By Jesse Allen - 17 Nov, 2020 - Comments: 0

NVMe controller for research Researchers at the Korea Advanced Institute of Science and Technology (KAIST) developed a non-volatile memory express (NVMe) controller for storage devices and made it freely available to universities and research institutions in a bid to reduce research costs. Poor accessibility of NVMe controller IP is hampering academic and industrial research, the team argue... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Nov, 2020 - Comments: 0

M&A Synopsys acquired Moortec, a provider of in-chip monitoring technology specializing in process, voltage and temperature (PVT) sensors. Moortec's sensors will be a key component to Synopsys' new Silicon Lifecycle Management (SLM) platform. "This acquisition accelerates the expansion of our SLM platform by providing our customers with a comprehensive data-analytics-driven solution for de... » read more

Blog Review: Nov. 11
By Jesse Allen - 11 Nov, 2020 - Comments: 0

Mentor's Chris Spear proposes mixing together the compactness of the field macro style with the preciseness of the do methods when writing a UVM transaction class. Cadence's Paul McLellan looks back at the history of EPROM, some of the difficulty with actually erasing it, and the subsequent development of EEPROM. Synopsys' Tuomo Untinen explains three WPA2 authentication vulnerabilities r... » read more

Power/Performance Bits: Nov. 9
By Jesse Allen - 09 Nov, 2020 - Comments: 0

Integrated transistor cooling Researchers at Ecole Polytechnique Fédérale de Lausanne (EPFL) created a single chip that combines a transistor and microfluidic cooling system for more efficient transistor heat management. The team focused on a co-design approach for the electrical and mechanical aspects of the chip, bringing the electronics and cooling design together and aiming to extract... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Nov, 2020 - Comments: 0

Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

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