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Blog Review: Nov. 25

FPGA complexity; next decade of semiconductors; CXL 2.0; adding functional safety.

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Mentor’s Harry Foster finds growing complexity in FPGA design by looking at the number of embedded microprocessors, asynchronous clock domains, and safety/security features in the 2020 Wilson Research Group Functional Verification Study.

Cadence’s Paul McLellan points to the interim SRC/SIA Decadal Plan for Semiconductors and five big shifts it identifies in information and communication technologies, from new requirements for analog hardware to security challenges associated with AI.

A Synopsys writer checks out the new CXL 2.0 specification, which introduces integrity & data encryption, and explains what a secure setup looks like and the strategies adopted by CXL.

Arm’s Naresh Menon explains ways to add functional safety to a CPU through software test libraries, an approach that uses software functions to provide hardware diagnostic capabilities for permanent faults and can be applied to existing designs.

Ansys’ Nilay Parikh finds a surge of interest in industrial additive manufacturing to alleviate pandemic-related shortages of PPE and test supplies, but notes that supply chain shortages also affected the base materials for 3D printing.

Rambus’ Frank Ferro and Joseph Rodriguez discuss selection criteria and implementation details for HBM2E memory, comparison to GDDR6, and price/performance tradeoffs to consider.

In a blog for SEMI, Sébastien Clerc of Yole Développement considers whether the increased demand for microfluidics will persist after the COVID-19 rush for testing kits and the potential for growth in other point-of-care diagnostics.

Silicon Labs’ Kevin Smith considers some of the reasons to use nested dual-loop PLLs and key considerations to keep in mind, such as the bandwidth relationship between the inner and outer loops and analyzing phase noise.

Plus, check out the blogs featured in the latest Systems & Design and Manufacturing, Packaging & Materials newsletters:

Editor in Chief Ed Sperling contends that as semiconductors push toward the most advanced nodes with new packaging, reliability is taking on a whole new dimension.

Executive Editor Mark LaPedus wonders if price increases are in store for wafers.

Quik-Pak’s Sam Sadri describes how to reduce handling and predict failures, and provides tips for dealing with complex packaging technologies.

Amkor’s Vineet Pancholi addresses test challenges in leading IC markets such as 5G, AI, and automotive.

Lam Research’s Nerissa Draeger observes that finFETs are reaching the end of their utility as challenges mount at the 5/3nm nodes, but new transistor types are on the horizon.

SEMI’s guest blogger Jean-Marc Philippe examines how Industry 4.0 technology is breathing new life into aging chipmaking equipment.

Coventor’s Timothy Yang explains how to use visibility etch modeling to compensate for challenging aspects of etch recipe development.

Technology Editor Brian Bailey takes a look back over 2020 to see what everyone has been reading and which subjects are the most important to you.

Cadence’s Frank Schirrmeister explains how new networking and architecture co-design opportunities are creating a fundamental shift in the data center.

Codasip’s Roddy Urquhart describes the effect of adding RISC-V extensions to both core size and codesize.

Mentor’s Abdellah Bakhali examines how to combine geometric and topological data for better reliability verification.

Synopsys’ Alan Courtay and Gobi Kengara Palayam Appavoo advocate using piecewise linear circuit models rather than models with full SPICE-level accuracy to perform earlier simulation.

OneSpin’s Rob van Blommestein argues that simulation-only verification is not enough to eliminate security weaknesses or vulnerabilities and can lead to critical bug escapes.

Tortuga Logic’s Jason Oberg warns that hardware vulnerabilities are becoming more widespread and costly, necessitating a common language for defining security weaknesses.



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