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Blog Review: Nov. 18

Mobile holograms; auto ECU consolidation; NAND flash; IoT software security.

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Arm’s Roberto Lopez Mendez finds that holographic displays can now be achieved on mobile processors thanks to recent algorithmic and computational advances.

Mentor’s Colin Walls examines the reasons the consolidate a number of automotive sub-systems onto a smaller number of powerful ECU to reduce complexity and increase system reliability.

Cadence’s Paul McLellan takes a look at the development of NAND flash and new types of emerging memories, including MRAM, ReRAM, and 3DXpoint.

Synopsys’ Taylor Armerding considers strategies for protecting IoT devices by building security and privacy into the software development life cycle.

In a blog for SEMI, Walt Custer of Custer Consulting finds that third-quarter world electronic equipment shipment growth showed a big improvement over the second quarter, but chip shipment and wafer foundry sale growth appears to be leveling off.

Ansys’ Jamie Gooch checks out the steps involved in building a digital twin of San Francisco’s Golden Gate Bridge that could be used to calculate forces on the bridge structures as the wind direction or velocity change.

Plus, check out the blogs highlighted in the latest Low Power-High Performance newsletter:

Editor in chief Ed Sperling predicts that Apple’s new chip is just the tip of a technological revolution.

Fraunhofer’s Andy Heinig foresees the need to move from classic encryption algorithms with increasing key lengths to communication based on entangled quanta.

Mentor’s Progyna Khondkar describes a method for building low-power verification platforms using UPF information models and dynamic objects.

Arm’s James Myers digs into the greatest challenge the Internet of Things faces – how those ‘things’ will be powered.

Rambus’ Joseph Rodriguez reviews why MIPI is no longer just about mobile phones.

Ansys’ Josh Akman walks through the early proactive steps that ensure that a design can be consistently manufactured with a minimum number of defects.

Cadence’s Paul McLellan looks into recently announced high-end processors that are pushing performance capabilities to the forefront.

Synopsys’ Rahul Deokar explains why process variability, physical effects, and the impact of interconnect are critical in timing analysis.

Moortec’s Tim Penhale-Jones anticipates that as geometries shrink, the ability to monitor what’s going on in a device is increasingly important.

OneSpin’s Sergio Marchese wonders, as new security vulnerabilities are discovered in automotive electronics, who is responsible for protecting his car? ISO/SAE 21434 may have an answer.

Synopsys’ Randy Fish addresses potential security risks associated with using high-speed interfaces such as PCIe or USB for scan chain access.



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