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The Challenge Of Balancing Performance And Accuracy For Advanced Node Timing Signoff

Process variability, physical effects, and the impact of interconnect are critical in timing analysis.

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As process nodes shrink, complexity, cost and overall risk expand. Process variability that once was once acceptable now becomes a critical item as operating voltage decreases. Simply adding design margin makes the chip non-competitive. Physical effects that were once ignored now become critical as well. The impact of interconnect can no longer be modeled based on simple circuit topology. Layout tools must be timing-aware and timing analysis tools must be layout-aware.

The effort required to build, operate and provide all the required modeling and infrastructure for advanced process nodes has also exploded. The number of foundries that can effectively address all these demands has seen a severe reduction as process nodes advance, as shown in the figure below.


Severe reduction in number of fabs.

Against this backdrop of high-cost and high-risk design, EDA software must deliver the required accuracy. Furthermore, due to the intense time and cost pressures involved, these tools must do the job with reasonable run times and compute resources. One of the most critical steps in this process is timing signoff. There is always significant focus on density and power optimization, but unless timing can be met the design will not succeed in its intended application. Let’s now examine some of the techniques used by the Synopsys PrimeTime solution to strike the right balance between performance and accuracy to meet the demands for advanced node timing signoff.

Parametric on-chip variation
Historically, if a chip passed timing at a “slow” corner and “fast” corner, timing was considered closed. Today, there are far too many timing variables and timing margins are far too tight for an approach like this to work. Instead, a statistical delay distribution approach is used that relies on delay/transition/constraint variation modeling. Parametric on-chip variation (POCV) techniques use values stored as statistical quantities and the distributions are propagated as independent random variables through the analysis.

To support enhanced accuracy, standard Liberty Variation Formats (LVFs) containing the early/late format as well as moments format are used with PrimeTime LVF flows. Moments format provides support for asymmetric or non-Gaussian distributions with the inclusion of statistical moments (standard deviation, skewness, and non-centered mean values). This facilitates enhanced timing correlation between the Synopsys IC Compiler II solution and PrimeTime. For example, in a PrimeTime versus SPICE correlation study in 5 nm technology operating at <0.5 V, PrimeTime was able to achieve a correlation with SPICE of between 1.6% standard deviations using the moments format.

Interconnect variation modeling
At advanced nodes, cell delay/variation margins continue to shrink. To improve accuracy, local variation by sigma and global variation by derate factors (for metals) are modeled. These derate factors include both a resistance factor and a capacitance factor. In the case of via variation, which is considered local, the modeling occurs with a separate file that provides a standard deviation per area for each via layer.

Multi-input switching
With conventional multi-input switching (MIS), coefficients are used to model these effects. This approximation breaks down for advanced nodes. An advanced MIS technique calculates the impact based on slew/load/skew of each input and supports most combinational cells. This approach exhibits improved correlation with SPICE when compared to less accurate MIS models. With PrimeTime’s advanced MIS technique, modeling has proven that waveforms produced using this technique can reach within 1% compared to SPICE models.

Improving performance
Path-based analysis (PBA) has advanced in efficiency and reduced pessimism since it emerged as a high-accuracy alternative to graph-based analysis (GBA). Enhancements to PBA include exhaustive PBA and infinity-mode exhaustive PBA, which takes advantage of massive multi-threading with smart path filtering technology and caching. One of the latest innovations in PBA is a graph-based refinement, which improves PBA runtime by 2X to 5X through an intensive re-analysis of critical regions of the timing graph.

Integrating machine learning
Machine learning (ML) technology can be used to generate its own training data and learn on the fly. This approach is low maintenance since it doesn’t require external training or additional resources. The ML algorithm balances runtime versus accuracy as a function of total negative slack (TNS). At higher levels of TNS, the ML path-based analysis method dramatically reduces runtime by 2X to 5X. As a design nears signoff, ML PBA runtime converges to that of exhaustive PBA and is fully signoff safe by construction. PrimeTime also offers this ML-based technology to deliver power recovery speedup, which provides a boost to power ECO operations by up to 4x.

Simultaneous multi-voltage
Simultaneous multi-voltage (SMV) is a technique used in PrimeTime that enables single run dynamic voltage and frequency scaling (DVFS) cross-domain analysis. This significantly speeds up analysis for designs with various voltage levels and clock frequencies. For instance, in a typical analysis with five voltage levels and five clock frequencies, there would be 25 corners to run. With SMV, these corners would all be completed in a single run.

Process rules aware fast ECO
As ECOs can substantially increase a design cycle, performing ECOs with less iterations can have a big impact on the schedule. With a more physically-aware ECO process, less iterations are needed for place and route tools to achieve ECO closure. PrimeTime uses a routability-aware ECO process, with power-grid–aware, pin-access–driven, and pin-track–alignment features. For 7nm and below, there are also other features that ensure ECO closure, including via ladders support, point touch rules support, and context-aware leakage.

The user interface
The usability of the graphical user interface (GUI) has a big impact on the overall productivity of any EDA tool. PrimeTime’s ECO GUI enables complete signoff-driven physical/layout editing, which includes full-chip-capacity density maps, useful in analyzing the impacts of ECO. This approach allows for interactive ECO editing, as edits in the design and moving cells in the ECO GUI provide immediate feedback on performance changes.

To learn more
This is a summary of ways to balance performance and accuracy for advanced node timing signoff. For more detailed information, download the white paper entitled Lower Process Nodes Drive Timing Signoff Software Evolution, or view on demand the webinar Advances in Timing Signoff to Address Today’s Design Challenges.



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