Power/Performance Bits: Nov. 17

NVMe controller for research
Researchers at the Korea Advanced Institute of Science and Technology (KAIST) developed a non-volatile memory express (NVMe) controller for storage devices and made it freely available to universities and research institutions in a bid to reduce research costs.

Poor accessibility of NVMe controller IP is hampering academic and industrial research, the team argues, and said that NVMe IP costs around $34,000 per month for research, with costs reaching approximately $84,000 for IP that can be modified.

The new NVMe controller technology, called OpenExpress, comprises a wide range of basic hardware IP and key NVMe IP cores. To examine its actual performance, the team made an NVMe hardware controller prototype using OpenExpress, and designed all logics provided by OpenExpress to operate at high frequency.

The FPGA memory card prototype developed using OpenExpress demonstrated increased input/output data processing capacity per second, supporting up to 7 gigabit per second (GB/s) bandwidth, which the team said makes it suitable for ultra-high speed and volume next generation memory device research.

Prototype board and floorplan of OpenExpress. (Image credit: Professor Myoungsoo Jung, KAIST)

In a test comparing various storage server loads on devices, the team’s FPGA also showed 76% higher bandwidth and 68% lower input/output delay compared to Intel’s new high performance SSD (Optane SSD), which is sufficient for many researchers studying systems employing future memory devices. Depending on user needs, silicon devices can be synthesized as well, which is expected to further enhance performance.

“With the product of this study being disclosed to the world, universities and research institutes can now use controllers that used to be exclusive for only the world’s biggest companies, at no cost,” said Professor Myoungsoo Jung from the School of Electrical Engineering at KAIST. “This is a meaningful first step in research of information storage device systems such as high-speed and volume next generation memory.”

The NVMe controller technology can be freely used and modified under the OpenExpress open-source end-user agreement for non-commercial use by all universities and research institutes.

More accurate DNNs
Researchers at North Carolina State University improved the performance of deep neural networks by combining what are usually two separate tasks.

“Feature normalization is a crucial element of training deep neural networks, and feature attention is equally important for helping networks highlight which features learned from raw data are most important for accomplishing a given task,” said Tianfu Wu, an assistant professor of electrical and computer engineering at NC State. “But they have mostly been treated separately. We found that combining them made them more efficient and effective.”

The new single module, called attentive normalization (AN), improved the accuracy of the system significantly while using negligible extra computational power.

To test their AN module, the researchers plugged it into four widely used neural network architectures: ResNets, DenseNets, MobileNetsV2 and AOGNets. They then tested the networks against two benchmarks: the ImageNet-1000 classification benchmark and the MS-COCO 2017 object detection and instance segmentation benchmark.

“We found that AN improved performance for all four architectures on both benchmarks,” Wu said. “For example, top-1 accuracy in the ImageNet-1000 improved by between 0.5% and 2.7%. And Average Precision (AP) accuracy increased by up to 1.8% for bounding box and 2.2% for semantic mask in MS-COCO.

“Another advantage of AN is that it facilitates better transfer learning between different domains,” Wu added. “For example, from image classification in ImageNet to object detection and semantic segmentation in MS-COCO. This is illustrated by the performance improvement in the MS-COCO benchmark, which was obtained by fine-tuning ImageNet-pretrained deep neural networks in MS-COCO, a common workflow in state-of-the-art computer vision.”

The researchers have released the source code publicly on GitHub.

Photonic ultrasound detector
Researchers at Helmholtz Zentrum München and the Technical University of Munich (TUM) built a tiny ultrasound detector based on miniaturized photonic circuits on top of a silicon chip. Targeted for super-resolution imaging, the detector is capable of visualizing much smaller features than standard ultrasound detectors.

Typically, ultrasound waves are detected using piezoelectric detectors, which convert the pressure from ultrasound waves into electric voltage. Imaging resolution is dependent on size, but shrinking them too much can impair sensitivity.

Instead of recording voltage from piezoelectric crystals, the new silicon waveguide-etalon detector (SWED) monitors changes in light intensity propagating through the miniaturized photonic circuits.

“This is the first time that a detector smaller than the size of a blood cell is used to detect ultrasound using the silicon photonics technology,” said Rami Shnaiderman, of both Helmholtz Zentrum München and TUM. “If a piezoelectric detector was miniaturized to the scale of SWED, it would be 100 million times less sensitive.”

The SWED size is about half a micron, making it 10,000 times smaller than the smallest piezoelectric detectors used in clinical imaging and 200 times smaller than the ultrasound wavelength used, allowing it to visualize features that are smaller than one micrometer. “The degree to which we were we able to miniaturize the new detector while retaining high sensitivity due to the use of silicon photonics was breathtaking,” said Prof. Vasilis Ntziachristos, of both Helmholtz Zentrum München and TUM.

The team said that mass production is feasible as the silicon platform is easily manufacturable. “We will continue to optimize every parameter of this technology – the sensitivity, the integration of SWED in large arrays, and its implementation in hand-held devices and endoscopes,” noted Shnaiderman.