Research Bits: Dec. 2


Ionothermoelectric cooling Researchers from the University of Osaka, University of Tokyo, and Japan's National Institute of Advanced Industrial Science and Technology proposed an ionothermoelectric cooling strategy for chips that enhances cooling by driving the flow of ions through nanoscale channels. “We fabricated a nanosized pore in a semiconductor membrane and surrounded the nanopore ... » read more

Chip Industry Technical Paper Roundup: Nov. 26


New technical papers recently added to Semiconductor Engineering’s library: [table id=494 /] Find more semiconductor research papers here. » read more

Chip Industry Technical Paper Roundup: Nov. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=492 /] Find more semiconductor research papers here. » read more

Edge AI Safety: Agentic AI Architecture That Leverages 3D To Integrate A Dedicated Safety Layer (Princeton, HKUST, NC State Univ.)


A new technical paper titled "3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence" was published by researchers at Princeton University, Hong Kong University of Science and Technology, and North Carolina State University. Abstract "AI systems have found a wide range of real-world applications in recent years. The adoption of edge artificial intelligence, ... » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)


A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

Chip Industry Technical Paper Roundup: Sept 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=477 /] Find more semiconductor research papers here. » read more

Critical Challenges and Opportunities Related to Polymer-Based Materials in Semiconductor Packaging (NIST, NC State, NREL et al)


A new technical paper titled "Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science" was published by researchers at the National Institute of Standards and Technology, North Carolina State University, National Renewable Energy Laboratory, ASE, Intel, Innocentrix, and Binghamton University. Abstract "This Perspective builds up... » read more

Research Bits: Sept. 8


Gallium oxide pn diodes Researchers at Nagoya University fabricated functional gallium oxide pn diodes that can carry twice as much electrical current as previous gallium oxide diodes and waste less energy than silicon-based diodes. The key challenge in making the pn diode was creating a stable p-type gallium oxide layer. While gallium oxide's crystal structure easily accepts the atoms need... » read more

Chip Industry Week in Review


AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Chip Industry Week In Review


ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

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