Chip Industry Technical Paper Roundup: Sept. 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

A HW-Based Correct Execution Environment Supporting Virtual Memory (Korea U., KAIST)


A new technical paper titled "A Hardware-Based Correct Execution Environment Supporting Virtual Memory" was published by researchers at Korea University, Korea Advanced Institute of Science and Technology and other universities. Abstract "The rapid increase in data generation has led to outsourcing computation to cloud service providers, allowing clients to handle large tasks without inve... » read more

Chip Industry Technical Paper Roundup: August 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=252 /] More ReadingTechnical Paper Library home » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs


A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

Research Bits: July 22


Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Research Bits: April 8


Annealing processor Researchers from the Tokyo University of Science designed a scalable, fully-coupled annealing processor with 4096 spins on a single board with 36 CMOS chips, with parallelized capabilities for accelerated solving of combinatorial optimization problems. "We want to achieve advanced information processing directly at the edge, rather than in the cloud, or performing prepro... » read more

3D-Integrated Neuromorphic Hardware With A Two-Level Neuromorphic “Synapse Over Neuron” Structure


A technical paper titled “3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration” was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and SK hynix. Abstract: "Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency... » read more

Directed Self-Assembly Finds Its Footing


Ten years ago, when the industry was struggling to deliver EUV lithography, directed self-assembly (DSA) roared to the forefront of research and development for virtually every manufacturer determined to extend the limits of 193i. It was the hot topic at of the 2012 SPIE Advanced Lithography Conference, with one attendee from Applied Materials comparing its potential to disrupt the industry to ... » read more

Chip Industry’s Technical Paper Roundup: August 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=124 /] More Reading Technical Paper Library home » read more

How Band Nesting Can Achieve Near-Perfect Optical Absorption In Just Two Layers Of TMD Materials


A technical paper titled “Achieving near-perfect light absorption in atomically thin transition metal dichalcogenides through band nesting” was published by researchers at University of Minnesota, University of Notre Dame, and Korea Advanced Institute of Science and Technology (KAIST). Abstract: "Near-perfect light absorbers (NPLAs), with absorbance, λ, of at least 99%, have a wide ... » read more

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