tag: DNNs

Photonic Chip With A 2D Programmable Waveguide (Boston U., UC Irvine, Yale)
By Technical Paper Link - 10 Dec, 2025 - Comments: 0

A new technical paper titled "Arbitrary control over multimode wave propagation for machine learning" was published by researchers at Boston University, UC Irvine, and Yale University. Abstract "Controlled multimode wave propagation can enable more space-efficient photonic processors than architectures based on discrete components connected by single-mode waveguides. Instead of defining d... » read more

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)
By Technical Paper Link - 02 Oct, 2025 - Comments: 0

A new technical paper titled "Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage" was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract "Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices... » read more

Energy-Aware DL: The Interplay Between NN Efficiency And Hardware Constraints (Imperial College London, Cambridge)
By Technical Paper Link - 20 May, 2025 - Comments: 0

A new technical paper titled "Energy-Aware Deep Learning on Resource-Constrained Hardware" was published by researchers at Imperial College London and University of Cambridge. Abstract "The use of deep learning (DL) on Internet of Things (IoT) and mobile devices offers numerous advantages over cloud-based processing. However, such devices face substantial energy constraints to prolong batte... » read more

More Efficient Side-Channel Analysis By Applying Two Deep Feature Loss Functions
By Technical Paper Link - 12 Dec, 2023 - Comments: 0

A technical paper titled “Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis” was published by researchers at Nanyang Technological University, Radboud University, and Delft University of Technology. Abstract: "This paper provides a novel perspective on improving the efficiency of side-channel analysis by applying two deep feature loss functions: Soft Nearest Neig... » read more

A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets
By Technical Paper Link - 08 Aug, 2023 - Comments: 0

A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

ML Automotive Chip Design Takes Off
By Ann Mutschler - 04 May, 2023 - Comments: 0

Machine learning is increasingly being deployed across a wide swath of chips and electronics in automobiles, both for improving reliability of standard parts and for the creation of extremely complex AI chips used in increasingly autonomous applications. On the design side, the majority of EDA tools today rely on reinforcement learning, a machine learning subset of AI that teaches a machine ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Memory and Energy-Efficient Batch Normalization Hardware
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training" was published by researchers at DGIST (Daegu Gyeongbuk Institute of Science and Technology). The work was supported by Samsung Research Funding Incubation Center. Abstract: "When training early-stage deep neural networks (DNNs), generating intermediate features via con... » read more

Complex Tradeoffs In Inferencing Chips
By John Koon - 17 Oct, 2022 - Comments: 0

Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Visual Fault Inspection Using A Hybrid System Of Stacked DNNs
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A technical paper titled "Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks" was published by researchers at Chemnitz University of Technology (Germany). According to the paper, "this contribution introduces a novel hybrid multistage system of stacked deep neural networks (SH-DNN) which allows the localization... » read more

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