More Efficient Side-Channel Analysis By Applying Two Deep Feature Loss Functions

A technical paper titled “Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis” was published by researchers at Nanyang Technological University, Radboud University, and Delft University of Technology. Abstract: "This paper provides a novel perspective on improving the efficiency of side-channel analysis by applying two deep feature loss functions: Soft Nearest Neig... » read more

A Search Framework That Optimizes Hybrid-Device IMC Architectures For DNNs, Using Chiplets

A technical paper titled “HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms” was published by researchers at Yale University. Abstract: "Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pr... » read more

ML Automotive Chip Design Takes Off

Machine learning is increasingly being deployed across a wide swath of chips and electronics in automobiles, both for improving reliability of standard parts and for the creation of extremely complex AI chips used in increasingly autonomous applications. On the design side, the majority of EDA tools today rely on reinforcement learning, a machine learning subset of AI that teaches a machine ... » read more

Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs

A technical paper titled "Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks" was published by researchers at KU Leuven and TU Munich. Abstract "To keep up with the ever-growing performance demand of neural networks, specialized hardware (HW) accelerators are shifting towards multi-core and chiplet architectures. So far, thes... » read more

Memory and Energy-Efficient Batch Normalization Hardware

A new technical paper titled "LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training" was published by researchers at DGIST (Daegu Gyeongbuk Institute of Science and Technology). The work was supported by Samsung Research Funding Incubation Center. Abstract: "When training early-stage deep neural networks (DNNs), generating intermediate features via con... » read more

Complex Tradeoffs In Inferencing Chips

Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Visual Fault Inspection Using A Hybrid System Of Stacked DNNs

A technical paper titled "Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks" was published by researchers at Chemnitz University of Technology (Germany). According to the paper, "this contribution introduces a novel hybrid multistage system of stacked deep neural networks (SH-DNN) which allows the localization... » read more

New Uses For AI In Chips

Artificial intelligence is being deployed across a number of new applications, from improving performance and reducing power in a wide range of end devices to spotting irregularities in data movement for security reasons. While most people are familiar with using machine learning and deep learning to distinguish between cats and dogs, emerging applications show how this capability can be use... » read more

Simulation Framework to Evaluate the Feasibility of Large-scale DNNs based on CIM Architecture & Analog NVM

Technical paper titled "Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines" from researchers at UCLA. Abstract "Recently, analog compute-in-memory (CIM) architectures based on emerging analog non-volatile memory (NVM) technologies have been explored for deep neural networks (DNNs) to improve scalability, speed, and energy efficiency. Such architectures, however, leverage ... » read more

Neuromorphic Chips & Power Demands

Research paper titled "A Long Short-Term Memory for AI Applications in Spike-based Neuromorphic Hardware," from researchers at Graz University of Technology and Intel Labs. Abstract "Spike-based neuromorphic hardware holds the promise to provide more energy efficient implementations of Deep Neural Networks (DNNs) than standard hardware such as GPUs. But this requires to understand how D... » read more

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