Alternative Text

Jesse Allen

  (all posts)
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 29 May, 2020 - Comments: 0

Tools & IP Arm unveiled several new processor IPs. Targeting next-gen smartphones, the Cortex-A78 CPU provides a 20% increase in sustained performance over Cortex-A77-based devices within a 1-watt power budget, and more efficient management of compute workloads and on-device ML. The Mali-G78 GPU provides a 25% increase in performance over the Malti-G77. It supports up to 24 cores and in... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2020 - Comments: 0

Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Power/Performance Bits: May 26
By Jesse Allen - 26 May, 2020 - Comments: 0

Warmer quantum computing Researchers at the University of New South Wales Sydney, Université de Sherbrooke, Aalto University, and Keio University developed a proof-of-concept quantum processor unit cell on a silicon chip that works at 1.5 Kelvin – 15 times warmer than current chip-based technology that uses superconducting qubits. "This is still very cold, but is a temperature that can b... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Power/Performance Bits: May 19
By Jesse Allen - 19 May, 2020 - Comments: 0

Neuromorphic magnetic nanowires Researchers from the University of Texas at Austin, University of Texas at Dallas, and Sandia National Laboratory propose a neuromorphic computing method using magnetic components. The team says this approach can cut the energy cost of training neural networks. "Right now, the methods for training your neural networks are very energy-intensive," said Jean Ann... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

Blog Review: May 13
By Jesse Allen - 13 May, 2020 - Comments: 0

Mentor's Neil Johnson considers when in a project certain verification methods should be deployed and the relative impact of techniques at a given point in subsystem design. Cadence's Paul McLellan looks back at the development of mobile standards with 2G, GSM, and the transition to all-digital transmission. Synopsys' Taylor Armerding highlights five online courses to boost your software ... » read more

Power/Performance Bits: May 11
By Jesse Allen - 11 May, 2020 - Comments: 0

Light-emitting silicon Researchers from the Eindhoven University of Technology, Friedrich-Schiller-Universität Jena, Johannes Kepler University, and Technische Universität München developed a silicon germanium alloy that can emit light, paving the way for a silicon laser that could be integrated for on-chip and chip-to-chip communication. Bulk silicon is extremely inefficient at emitting... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 May, 2020 - Comments: 0

Tools & IP Ansys' RedHawk-SC multiphysics signoff software was certified for all TSMC advanced process technologies, including N16, N12, N7, N6 and N5. The certification includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis and statistical EM budgeting analysis. Aldec launched a new FPGA accelerator board for high performance... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy