Week In Review: Design, Low Power

Silvaco buys CWS interference analysis assets; electronic-photonic co-design; 4 Gbps HBM2E memory interface.


Silvaco acquired the assets of Coupling Wave Solutions (CWS), including IP, patents, and analysis technologies. CWS provides tools for system-level interference analysis of complex SoCs that integrate analog, RF, and digital blocks. Silvaco said that the acquisition expands the company’s portfolio to address RF SOI (Silicon on Insulator) substrate analysis to accurately model and simulate noise interference in circuits used in 5G and IoT applications. The CTO of CWS, Francois Clement, has also joined Silvaco. CWS was founded in 2004 and based in Grenoble, France.

Tools & IP
Synopsys unveiled OptoCompiler, a solution for photonic integrated circuit (PIC) design, layout implementation, and verification. Aimed at enabling electronic-photonic co-design, OptoCompiler combines schematic-driven layout and advanced photonic layout synthesis in a single platform and includes features for hierarchical design plus the ability to use dedicated native photonic simulators. Inphi Corporation noted it has used the platform in multiple tapeouts.

Arasan Chip Systems released MIPI I3C Host Controller Interface (I3C HCI) Host IP and I3C Device IP compliant to the MIPI I3C HCI Specification Ver 1.1. Arasan also provides a Linux software stack compatible with its I3C HCI Host IP and I3C HDK.

Rambus said it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with HBM2E DRAM from SK Hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. Alchip led the interposer and package substrate design.

CAST and Fraunhofer IPMS teamed up on a new option for their CAN 2.0 and CAN FD Controller IP Core that adds support for the evolving CAN XL standard. Aimed at early adopters, the new CAN XL option for CAST’s CAN-CTRL IP core adds support for 610-1 CAN XL data link layer and physical signaling specification. It includes all the expected technical functions and features, plus any future updates required to match the final ratified ISO specification.

DSP Group selected Synopsys’ DesignWare ARC EM5D Processor IP for its DBMC2-TWS advanced adaptive processing audio codec for true wireless stereo (TWS) headsets. DSP Group cited the IP’s high-efficiency control and signal processing capabilities, and the company also used the DesignWare ARC MetaWare Development Toolkit for DSP software development for its audio and voice processing SoC.

Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The Embedded Vision Summit is coming up Sept. 15-25 as a virtual conference. The program will focus on the latest applications, techniques, technologies, and opportunities in computer vision and visual AI with keynotes, exhibits, and workshops.

Ansys will host its IDEAS Digital Forum on Sept. 23-24 with discussions of key technology and market trends as well as sessions on the latest methodologies and best practices for low-power chip design, 3DIC analysis, power integrity signoff, and on-chip electromagnetics.

VSDOpen, a virtual event dedicated to open source EDA and designs, will take place Oct. 10 with workshops available Oct. 7-9. Topics will include RISC-V in India, open IP designs, and what can be learned from the open source software movement.

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