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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Week In Review: Design, Low Power
By Jesse Allen - 05 Jun, 2020 - Comments: 1

Tools & IP Synopsys introduced its DesignWare USB4 IP solution consisting of controllers, routers, PHYs, and verification IP. It supports USB4, DisplayPort with HDCP 2.3 security, PCI Express, and Thunderbolt 3 connectivity protocols through USB Type-C connectors and cables. The USB4 IP operates at up to 40 Gbps, twice the maximum data rate of USB 3.2, and is backwards compatible with USB 3... » read more

Blog Review: June 3
By Jesse Allen - 03 Jun, 2020 - Comments: 0

Cadence's Paul McLellan takes a look at how Ethernet came to dominate wired networking and is now taking on automotive to provide the bandwidth necessary for the increasing number of sensors in modern vehicles. Mentor's Colin Walls notes the difficulty of assessing the quality of software, some key areas to pay attention to when assessing quality or trying to write quality code, and the bottom... » read more

Power/Performance Bits: June 2
By Jesse Allen - 02 Jun, 2020 - Comments: 0

Neuromorphic memristor Researchers at the University of Massachusetts Amherst used protein nanowires to create neuromorphic memristors capable of running at extremely low voltage. A challenge to neuromorphic computing is mimicking the low voltage at which the brain operates: it sends signals between neurons at around 80 millivolts. Jun Yao, an electrical and computer engineering researcher at ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 May, 2020 - Comments: 0

Tools & IP Arm unveiled several new processor IPs. Targeting next-gen smartphones, the Cortex-A78 CPU provides a 20% increase in sustained performance over Cortex-A77-based devices within a 1-watt power budget, and more efficient management of compute workloads and on-device ML. The Mali-G78 GPU provides a 25% increase in performance over the Malti-G77. It supports up to 24 cores and in... » read more

Blog Review: May 27
By Jesse Allen - 27 May, 2020 - Comments: 0

Mentor's Neil Johnson takes a look at achieving a practical verification methodology starting with an exclusively constrained random flow and building up by adding techniques and gauging the consequences. Cadence's Paul McLellan explains the history of neural networks and how we've been trying to mimic the brain for decades, only to see funding dry up until a sudden resurgence of annotated i... » read more

Power/Performance Bits: May 26
By Jesse Allen - 26 May, 2020 - Comments: 0

Warmer quantum computing Researchers at the University of New South Wales Sydney, Université de Sherbrooke, Aalto University, and Keio University developed a proof-of-concept quantum processor unit cell on a silicon chip that works at 1.5 Kelvin – 15 times warmer than current chip-based technology that uses superconducting qubits. "This is still very cold, but is a temperature that can b... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 May, 2020 - Comments: 0

Tools & IP Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIP... » read more

Blog Review: May 20
By Jesse Allen - 20 May, 2020 - Comments: 0

Synopsys' Jonathan Knudsen demystifies fuzzing techniques and why the process of sending targeted, intentionally invalid data is important to determining security. Mentor's Chris Spear explains both the potential benefits and challenges of the UVM Configuration Database and guidelines to improve performance. Cadence's Paul McLellan continues the look back at mobile history with the beginn... » read more

Power/Performance Bits: May 19
By Jesse Allen - 19 May, 2020 - Comments: 0

Neuromorphic magnetic nanowires Researchers from the University of Texas at Austin, University of Texas at Dallas, and Sandia National Laboratory propose a neuromorphic computing method using magnetic components. The team says this approach can cut the energy cost of training neural networks. "Right now, the methods for training your neural networks are very energy-intensive," said Jean Ann... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 May, 2020 - Comments: 0

Tools & IP Synopsys released a range of IP for TSMC's 5nm process technology. It includes interface PHY IP such as 112G/56G Ethernet, Die-to-Die, PCIe 5.0, CXL, and CCIX; memory interface IP for DDR5, LPDDR5, and HBM2/2E; die-to-die PHYs for 112G USR/XSR connectivity and High-Bandwidth Interconnect; and foundation IP including logic libraries, multi-port memory compilers, and TCAMs. Sma... » read more

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