Week In Review: Design, Low Power

New VIP from data center to auto; FPGA inferencing; TSMC certifications; Synopsys Q2.


Tools & IP
Cadence unveiled ten two verification IP (VIP) to support hyperscale data centers, automotive, and consumer and mobile applications. The new VIPs include complete bus functional models, integrated protocol checks and coverage models, and a specification-compliant verification plan. The VIPs cover CXL, HBM3, Ethernet 802.3ck, CSI-2 3.0, MIPI I3C 1.1, TileLink, eUSB2, UFS 3.1, MIPI SPMI, and MIPI RFFE v3.0.

Microchip uncorked a toolkit to make it easier to implement inferencing algorithms in the company’s PolarFire FPGAs. The VectorBlox Accelerator SDK allows developers to code in C/C++ and program neural networks without prior FPGA design experience, can execute models in TensorFlow and the open neural network exchange (ONNX) format, supports Linux and Windows, and includes a bit accurate simulator. Neural network IP is included.

S2C announced its new cloud based prototyping system. The Prodigy Cloud System is implemented with Intel’s Stratix 10 GX 10M FPGA and Xilinx’s Virtex UltraScale VU440 FPGA. It is scalable up to 2.5 billion logic gates over 32 FPGAs in single standard server rack.

Cadence debuted 56G long-reach PAM4 SerDes IP on TSMC’s N7 and N6 process technologies. The IP provides 36db+ insertion loss using multi-rate DSP technology, programmable power configurations, and data recovery. It also supports an industrial temperature range, CPRI data rate, and per-lane PLL for 5G applications.

Synopsys’ digital and custom design platforms were certified for TSMC’s N6 and N5 process technologies. Tools for HPC and mobile design flows were updated to enhance density, operating frequency, and power consumption, as well as improved to support ultra-low VDD requirements for low power consumption mobile and 5G designs.

Mentor received certification for a range of IC design tools, including Calibre and Analog FastSPICE, for TSMC’s N5 and N6 process technologies. Additionally, the AFS platform now supports TSMC’s mobile and HPC design platform, and Calibre’s 3DSTACK packaging tools support CoWoS packaging technology.

Blue Ocean Smart System licensed Arteris IP’s FlexNoC Interconnect IP and the accompanying AI Package for use in next generation SoC hardware accelerator for AI neural network inference and training. Blue Ocean cited the ability to construct complex high frequency and high bandwidth on-chip interconnects that were backend friendly for easier timing closure.

Fuji Xerox adopted Synopsys’ ZeBu Server emulation system for software development and performance tuning of its next-generation multifunction printer SoC. Fuji Xerox said the system accelerated application software development by over two months.

Organizations & People
Ansys, Dell Technologies, Lendlease, and Microsoft joined the Object Management Group in forming the Digital Twin Consortium. The new open membership organization will aim to drive consistency in vocabulary, architecture, security and interoperability to help advance the use of digital twin technology across different industries, as well as set roadmaps and industry guidelines.

Cadence CEO Lip-Bu Tan has been nominated for a seat on the Softbank board of directors. Softbank CFO Yoshimitsu Goto and Yuko Kawamoto of the Waseda Business School have also been nominated. Alibaba co-founder Jack Ma will be resigning from the Softbank board.

Synopsys reported second quarter 2020 financial results with revenue of $861.3 million, up 3% from the same quarter last year. On a GAAP basis, income was $0.71 per share for Q2 2020, down 7.8% from $0.77 per share in Q2 2020. Non-GAAP income was $1.22 per share for the quarter, up 5.2% from $1.16 per share the same quarter last year. The company maintained full year 2020 revenue guidance and raised non-GAAP EPS.

Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead?

Video: Take a look at the design side of advanced packaging and why it is still so difficult, in Rising Package Complexity.

Ansys will host the Simulation World virtual conference on June 10 & 11. Focused on multiphysics simulation across many sectors, there will be a dedicated Semiconductor Track and several industry tracks devoted to 5G, industrial IoT, electrification, and autonomous vehicles.

The ESD Alliance will host its 2020 CEO Outlook as a virtual event on June 17 at 10:30 a.m. PST. This year’s panel features Arm’s Simon Segars, Joseph Sawicki of Mentor, OneSpin’s Raik Brinkmann, John Kibarian from PDF Solutions, Prakash Narain of Real Intent, and Silvaco’s Babak Taheri. The panelists will discuss the impact of COVID-19 on the industry, along with major new trends and potential opportunities.

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. More details on the new virtual format will be available at a later date.

Arm TechCon has been renamed Arm DevSummit and will be held virtually October 5-9, 2020. The call for papers and presentations is now open through June 9.

If you have an event planned but not sure how to start moving it online, ACM published a report detailing some best practices for virtual conferences. It discusses the tasks required of organizers, platforms, and financial considerations, alongside examples of conferences that have gone virtual and lessons learned from their experiences.

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