Author's Latest Posts

Efficient Noise Analysis For Complex Non-Periodic Analog/RF Blocks

By Mentor, a Siemens Business - 25 Jun, 2014 - Comments: 0

Noise minimization is a required design objective for advanced analog and RF circuits. Unlike digital circuits, where noise is a second-order effect, noise in analog and RF circuits directly affects system performance metrics such as signal to noise ratio (SNR) and bit error rate (BER). Effective design optimization in the presence of random device noise is challenging because the noise sources... » read more

Root Cause Deconvolution

By Mentor, a Siemens Business - 19 Jun, 2014 - Comments: 0

Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by ... » read more

As Nodes Advance, So Must Power Analysis

By Mentor, a Siemens Business - 12 Jun, 2014 - Comments: 0

By Chetandeep Singh and Ravi Tangirala Smaller geometry nodes offer cost and performance advantages that encourage their adoption. Yet they present a new set of challenges for IC manufacturers: Though transistors are smaller, they leak more current. This is an important issue as the demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing shifts th... » read more

Internet of Things Design Considerations For Embedded Connected Devices

By Mentor, a Siemens Business - 11 Jun, 2014 - Comments: 0

Embedded connectivity has been around since the early days of M2M. But what is new are the many complexities and emerging standards embedded system developers need to know if they are to design the latest IoT device. This paper delves into many of the key considerations developers need to know and discusses the critical areas of IoT security and connectivity along with the importance of a prove... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation

By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

Divide And Conquer: Hierarchical DFT For SoC Designs

By Mentor, a Siemens Business - 14 May, 2014 - Comments: 0

Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is availabl... » read more

DFM Success At SMIC

By Mentor, a Siemens Business - 28 May, 2013 - Comments: 0

Jeff Wilson As any integrated circuit (IC) designer knows, design rules are the “first line of defense” foundries provide in the effort to ensure all IC designs are ultimately manufacturable. Coming in a close second, design for manufacturing (DFM) rules enable designers to maximize design capabilities and performance while minimizing or optimizing the use of chip space. At today’s ad... » read more

Three DFM “Litho” Checkpoints at SMIC

By Mentor, a Siemens Business - 03 Apr, 2012 - Comments: 0

Design for manufacturing (DFM) has been an industry buzz word for several years, but now that it is an expected part of every design flow at 40nm and below, we are seeing how the concept of DFM can be successfully deployed. For example, Semiconductor Manufacturing International Corporation (SMIC), one of the world’s largest semiconductor foundries, has established a process for litho checking... » read more

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