DFM Success At SMIC

DFM processes are no longer optional at advanced nodes, and they are now required by manufacturers to create efficient, high-performance chips.

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Jeff Wilson
As any integrated circuit (IC) designer knows, design rules are the “first line of defense” foundries provide in the effort to ensure all IC designs are ultimately manufacturable. Coming in a close second, design for manufacturing (DFM) rules enable designers to maximize design capabilities and performance while minimizing or optimizing the use of chip space.

At today’s advanced nodes, many DFM processes are no longer optional as manufacturers have realized the benefits of going beyond strict physical manufacturability concerns to emphasize the production of efficient and high-performing chip products. At Semiconductor Manufacturing International Corp. (SMIC), a centralized organization has been developed specifically to manage, control and perform quality assurance (QA) for all design and DFM rules for all technologies offered by SMIC. This QA process includes Concurrent Versions System (CVS) regression test system that performs nightly compares on design rules to identify any mismatches, and Calibre EDA tools for physical and electrical verification/signoff.

The general configuration of the SMIC CVS regression test system is shown in Figure 1. This proactive technology enables high-yield results by providing the comprehensive DFM service flows and model kits needed to ensure DFM compliance and optimization during the verification and tapeout process. In addition, it ensures that SMIC intellectual property (IP) and cell libraries remain DFM-compliant, regardless of changes to DFM rules and processes.


Figure 1. CVS regression test flow at SMIC.

SMIC collaborates with EDA vendors on DFM implementation and optimization through a variety of tools and processes. In particular, we’re going to take a closer look at how SMIC implemented an advanced fill process that ensures improved planarity before manufacturing.

Chemical-mechanical polishing (CMP) is the physical process by which the surface of a chip is “smoothed” during manufacturing. By predicting and altering the design to minimize surface variation before the actual manufacturing process, designers can improve both final yield and time to market. SMIC combines its CMP simulation results with the SmartFill functionality included in the Calibre YieldEnhancer tool to highlight potential CMP effects throughout the layout and provide advanced automated fill solutions that enable designers to achieve their planarity goals while minimizing the amount of fill shapes added to a layout. This blend of simulation and an advanced filling process reduces resistance variability while minimizing capacitance.

SMIC currently uses this combination of DFM techniques at 40nm processes, and work is well underway on their 28nm process. Probable post-CMP “hotspots” are identified and analyzed with respect to process corners and pre-defined “killer error” criteria. These hotspots are then reported to DFM engineers and other users, as necessary. SMIC also provides DFM action guidance to assist their customers in fixing errors and modifying layouts to improve manufacturing results.

To date, more than 50 designs have been checked with SMIC’s CMP-DFM flow. Examples of typical issues found and corrected are shown in Figure 2.


Figure 2. Typical CMP issues include dishing hotspots and unacceptable metal thickness at the edges.


As part of their future DFM action guidance, SMIC is working on automatic CMP-DFM fixing flows that integrate the “smart” fill functionality with commercial place and route flows. This flow will provide the advanced fill quality of results in the user’s design environment.

SMIC also uses “model-based dummy fill” for enhanced dummy fill insertion. A full model-based fill solution requires calling a CMP model to simulate the CMP process and results, which can be time-consuming. The Calibre SmartFill process is rule-based, in that it uses design rules and targets, but it combines these with a sophisticated analysis engine that provides built-in analysis capabilities and delivers a correct by construction solution. By leveraging the CVS flow, SMIC can reduce the burden on their customers, but still provide the DFM learning by validating changes made to the fill deck. Together, these resources provide an advanced fill solution that is much faster than a true model-based solution, but with the desired improvements.

The Calibre SmartFill process employs a min-variance algorithm, which can be applied to either blocks or full chips. Correct-by-construction capabilities analyze items such as layout density (including gradient) and polygon perimeters to ensure that the insertion of dummy metal will be optimized for each layout (Figure 3). SMIC provides this advanced fill solution in tapeout flows via their DFM Service. More importantly, designers can obtain the same utilities from SMIC to perform their own DFM-aware dummy fill and all related physical design and verification, which is now expected by the industry for advanced logic designs.


Figure 3. Using advanced fill technology to perform tiling at each metal layer on a 40 nm chip (2.2m x 1.6m).


The post-fill GDS results are shown in Figure 4, while detailed comparisons are shown in Figures 5-8.


Figure 4. When compared to a traditional rule-based fill solution, the advanced fill process results in 1.6 to 4 times better DRC compliance, in terms of the number of violations of density rules.



Figure 5. The advanced fill results show a much sharper density distribution, as well as a smaller number of fill patterns.



Figure 6. In density gradient results, the advanced fill solution provides a sharper density gradient distribution.



Figure 7. For perimeter gradient results, the advanced fill results have a much sharper perimeter distribution, and create a smoother post-ECP copper topography.



Figure 8. The advanced fill solution generates the best copper topography on silicon, compared to other solutions (such as router-based fill approaches).



Figure 9. The test chip is a DS standard cell IP, and the total chip window size is 3460 um x 6980 um.



Figure 10. Looking at the silicon atomic force profiling (AFP) data after CMP was applied to Metal1, the advanced fill whole chip topography post-M1 CMP is better than the results from a traditional dummy fill approach.


Figure 11. Reviewing silicon AFP data after CMP was applied to Metal2, the advanced fill whole chip topography post-M2 CMP is comparable to that of rule-based fill.

As the output from CMP simulation shows, using an advanced fill deck improves the planarity of ICs and validates the correct-by-construction solution. But improving planarity in the manufacturing process is just one part of SMIC’s CVS flow.

Other critical parts of the CVS flow include reducing the yield impact from vias, and the impact of lithography. The yield loss caused by less-than-ideal via structures continues to be a concern. The SMIC CVS flow uses DFM scoring capabilities to identify a number of potentially weak spots in the layout, including via structures. This scoring is followed by the application of via optimization to improve yield by modifying the layout. The robustness of via structures can be enhanced through the doubling of the via, or by increasing the metal overlapping the vias. The DFM scoring deck can validate the improvements made to the layout.

Another important area to consider is the impact from lithography. A lithography analysis tool estimates the effect of lithography on the layout, and provides editing hints to the full custom designer, or an automated solution that feeds forward lithographic hotspot information to place and route tools. SMIC uses its CVS flow as part of a continuous improvement process to ensure a constant emphasis on obtaining the best results possible, in the most efficient manner and in the least amount of time.
By evaluating the results of SMIC’s use of automated analysis and design modification for fill and via optimization as part of its DFM Services and DFM capabilities, it is clear that DFM technologies are no longer just a “nice to have” part of the layout design and verification process. Companies that employ DFM service flows and model kits can reap a multitude of benefits, including improved results, better products, and reduced time to market. With all it has to offer, DFM has become an integral part of the IC process.

—Jeff Wilson is a DFM product marketing manager in the Calibre organization at Mentor Graphics.